
Chapter 12 Pulse-Width Modulator (PWM8B6CV1) Block Description
Freescale Semiconductor
MC9S12C-Family / MC9S12GC-Family
357
Rev 01.24
12.3.2.5
PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains six control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a 1, the corresponding PWM output will be center
aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference
detailed description of the PWM output modes.
Table 12-5. PWMPRCLK Field Descriptions
Field
Description
6:5
PCKB[2:0]
Prescaler Select for Clock B — Clock B is 1 of two clock sources which can be used for channels 2 or 3. These
three bits determine the rate of clock B, as shown in Table 12-6. 2:0
PCKA[2:0]
Prescaler Select for Clock A — Clock A is 1 of two clock sources which can be used for channels 0, 1, 4, or 5.
These three bits determine the rate of clock A, as shown in
Table 12-7.Table 12-6. Clock B Prescaler Selects
PCKB2
PCKB1
PCKB0
Value of Clock B
0
Bus Clock
0
1
Bus Clock / 2
0
1
0
Bus Clock / 4
0
1
Bus Clock / 8
1
0
Bus Clock / 16
1
0
1
Bus Clock / 32
1
0
Bus Clock / 64
1
Bus Clock / 128
Table 12-7. Clock A Prescaler Selects
PCKA2
PCKA1
PCKA0
Value of Clock A
0
Bus Clock
0
1
Bus Clock / 2
0
1
0
Bus Clock / 4
0
1
Bus Clock / 8
1
0
Bus Clock / 16
1
0
1
Bus Clock / 32
1
0
Bus Clock / 64
1
Bus Clock / 128