參數(shù)資料
型號(hào): MC9328MXLDVF20
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類: 微處理器
英文描述: i.MX Integrated Portable System Processor
中文描述: i.MX處理器集成的便攜式系統(tǒng)
文件頁數(shù): 73/96頁
文件大?。?/td> 1495K
代理商: MC9328MXLDVF20
Specifications
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
73
3.17 Pulse-Width Modulator
The PWM can be programmed to select one of two clock signals as its source frequency. The selected clock signal
is passed through a divider and a prescaler before being input to the counter. The output is available at the pulse-
width modulator output (PWMO) external pin.
Figure 56. PWM Output Timing Diagram
11
MS_BS delay time
1
3
ns
12
MS_SDIO output delay time
1,2
3
ns
13
MS_SDIO input setup time for MS_SCLKO rising edge (RED bit = 0)
3
18
ns
14
MS_SDIO input hold time for MS_SCLKO rising edge (RED bit = 0)
3
0
ns
15
MS_SDIO input setup time for MS_SCLKO falling edge (RED bit = 1)
4
23
ns
16
MS_SDIO input hold time for MS_SCLKO falling edge (RED bit = 1)
4
0
ns
1.
2.
Loading capacitor condition is less than or equal to 30pF.
An external resistor (100 ~ 200 ohm) should be inserted in series to provide current control on the MS_SDIO pin,
because of a possibility of signal conflict between the MS_SDIO pin and Memory Stick SDIO pin when the pin
direction changes.
If the MSC2[RED] bit = 0, MSHC samples MS_SDIO input data at MS_SCLKO rising edge.
If the MSC2[RED] bit = 1, MSHC samples MS_SDIO input data at MS_SCLKO falling edge.
3.
4.
Table 33. PWM Output Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
1
System CLK frequency
1
0
87
0
100
MHz
2a
Clock high time
1
3.3
5/10
ns
2b
Clock low time
1
7.5
5/10
ns
Table 32. MSHC Signal Timing Parameter Table (Continued)
Ref No.
Parameter
Minimum
Maximum
Unit
System Clock
2a
1
PWM Output
3b
2b
3a
4b
4a
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