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MC9328MX21 Technical Data, Rev. 3.4
10
Freescale Semiconductor
Signal Descriptions
PC_RST
PCMCIA Reset output signal. This signal is multiplexed with NFRB signal of NF.
PC_OE
PCMCIA Memory Read Enable output signal asserted during common or attribute memory read cycles.
This signal is multiplexed with NFALE signal of NF.
PC_WE
PCMCIA Memory Write Enable output signal asserted during common or attribute memory cycles. This
signal is shared with RW of the EIM.
PC_VS1
PCMCIA Voltage Sense1 input signal. This signal is multiplexed with NFIO[2] signal of NF.
PC_VS2
PCMCIA Voltage Sense2 input signal. This signal is multiplexed with NFIO[1] signal of NF.
PC_BVD1
PCMCIA Battery Voltage Detect1 input signal. This signal is multiplexed with NFIO[0] signal of NF.
PC_BVD2
PCMCIA Battery Voltage Detect2 input signal. This signal is multiplexed with NF_WE signal of NF.
PC_SPKOUT
PCMCIA Speaker Out output signal. This signal is multiplexed with PWMO signal.
PC_REG
PCMCIA Register Select output signal. This signal is shared with EB2 of EIM.
PC_CE1
PCMCIA Card Enable1 output signal. This signal is multiplexed with NFCE signal of NF.
PC_CE2
PCMCIA Card Enable2 output signal. This signal is multiplexed with NFWP signal of NF.
PC_IORD
PCMCIA IO Read output signal. This signal is shared with EB3 of EIM.
PC_IOWR
PCMCIA IO Write output signal. This signal is shared with OE signal of EIM.
PC_WP
PCMCIA Write Protect input signal. This signal is multiplexed with NFIO[3] signal of NF.
PC_POE
PCMCIA Output Enable signal to enable voltage translation buffers and transceivers. This signal is
multiplexed with NFCLE signal of NF.
PC_RW
PCMCIA Read Write output signal to control external transceiver direction. Asserted high for read
access and negated low for write access. This signal is multiplexed with NFRE signal of NF.
PC_PWRON
PCMCIA input signal to indicate that the card power has been applied and stabilized.
CSPI
CSPI1_MOSI
Master Out/Slave In signal
CSPI1_MISO
Master In/Slave Out signal
CSPI1_SS[2:0]
Slave Select (Selectable polarity) signal. CSPI1_SS2 is also multiplexed with USBG_RXDAT and
CSPI1_SS1 is multiplexed with EXT_DMAGRANT.
CSPI1_SCLK
Serial Clock signal
CSPI1_RDY
Serial Data Ready signal. Also multiplexed with EXT_DMAREQ.
CSPI2_MOSI
Master Out/Slave In signal. This signal is multiplexed with USBH2_TXDP signal of USB OTG.
CSPI2_MISO
Master In/Slave Out signal. This signal is multiplexed with USBH2_TXDM signal of USB OTG.
CSPI2_SS[2:0]
Slave Select (Selectable polarity) signals. These signals are multiplexed with USBH2_FS,
USBH2_RXDP and USBH2_RXDM signal of USB OTG
CSPI2_SCLK
Serial Clock signal. This signal is multiplexed with USBH2_OE signal of USB OTG
CSPI3_MOSI
Master Out/Slave In signal. This signal is multiplexed with SD1_CMD.
CSPI3_MISO
Master In/Slave Out signal. This signal is multiplexed with SD1_D0.
CSPI3_SS
Slave Select (Selectable polarity) signal multiplexed with SD1_D3.
CSPI3_SCLK
Serial Clock signal. This signal is multiplexed with SD1_CLK.
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes