參數(shù)資料
型號(hào): MC9328MX21CJM
廠商: Freescale Semiconductor
文件頁數(shù): 13/100頁
文件大?。?/td> 0K
描述: MPU I.MX21 289-MAPBGA
特色產(chǎn)品: MC9328MX21 Multimedia Processor
標(biāo)準(zhǔn)包裝: 90
系列: i.MX21
核心處理器: ARM9
芯體尺寸: 32-位
速度: 266MHz
連通性: 1 線,EBI/EMI,I²C,IrDA,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 192
程序存儲(chǔ)器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.45 V ~ 3.3 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 289-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 732 (CN2011-ZH PDF)
MC9328MX21 Technical Data, Rev. 3.4
2
Freescale Semiconductor
Introduction
For cost sensitive applications, the NAND Flash controller allows the use of low-cost NAND Flash
devices to be used as primary or secondary non-volatile storage. The on-chip error correction code (ECC)
and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks. WLAN,
Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers.
The device is packaged in a 289-pin MAPBGA.
Figure 1. i.MX21 Functional Block Diagram
1.1
Conventions
This document uses the following conventions:
OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
Logic level one is a voltage that corresponds to Boolean true (1) state.
Logic level zero is a voltage that corresponds to Boolean false (0) state.
To set a bit or bits means to establish logic level one.
To clear a bit or bits means to establish logic level zero.
Connectivity
ARM9 Platform
System Control
Enhanced Multimedia Accelerator
(eMMA)
Standard System I/O
Memory Interface
ARM926EJ-
Internal Con-
Clock Manage-
I2C
UART x
1-WIRE
IrDA
USB OTG/ 2
SDRAM
C
EIM/BMI
NFC
i.MX21
CSPI x 3
Human Interface
Audio Mux
SSI x 2
JTAG/Multi-
System
Timers x
WDOG
RT
DMAC
GPI
PWM
SLCD Control-
Key-
D
I Cache
MAX
MM
Bus Con-
Memory Con-
Pre- and Post- Process-
Video Accelera-
Memory Expansion
MMC/SD x 2
PCMCIA/
LCD Controller
CSI
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