參數(shù)資料
型號(hào): MC9328MX1VM20R2
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 95/100頁(yè)
文件大?。?/td> 0K
描述: IC MCU I.MX 200MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MX1
核心處理器: ARM9
芯體尺寸: 32-位
速度: 200MHz
連通性: EBI/EMI,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 110
程序存儲(chǔ)器類(lèi)型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 256-MAPBGA
包裝: 帶卷 (TR)
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
94
Freescale Semiconductor
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
4.17.2
Non-Gated Clock Mode
Figure 70 shows the timing diagram when the CMOS sensor output data is configured for negative edge
and the CSI is programmed to received data on the positive edge. Figure 71 shows the timing diagram
when the CMOS sensor output data is configured for positive edge and the CSI is programmed to received
data in negative edge. The parameters for the timing diagrams are listed in Table 43.
Figure 70. Sensor Output Data on Pixel Clock Falling Edge
CSI Latches Data on Pixel Clock Rising Edge
Figure 71. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
Table 43. Non-Gated Clock Mode Parameters
Ref No.
Parameter
Min
Max
Unit
1
csi_vsync to csi_pixclk
180
ns
2
csi_d setup time
1
ns
VSYNC
PIXCLK
DATA[7:0]
Valid Data
1
2
3
4
5
6
VSYNC
PIXCLK
DATA[7:0]
Valid Data
1
2
3
4
5
6
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