參數(shù)資料
型號: MC9328MX1CVH15
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: i.MX Integrated Portable System Processor
中文描述: i.MX處理器集成的便攜式系統(tǒng)
文件頁數(shù): 66/96頁
文件大?。?/td> 1495K
代理商: MC9328MX1CVH15
MC9328MX1 Advance Information, Rev. 4
66
Freescale Semiconductor
Specifications
Figure 49. Timing Diagrams at Data Transfer Mode
Figure 50 on page 67 shows basic read operation timing. In a read operation, the sequence starts with a single block
read command (which specifies the start address in the argument field). The response is sent on the SD_CMD lines
as usual. Data transmission from the card starts after the access time delay N
AC
, beginning from the last bit of the
read command. If the system is in multiple block read mode, the card sends a continuous flow of data blocks with
distance N
AC
until the card sees a stop transmission command. The data stops two clock cycles after the end bit of
the stop command.
Timing of command sequences (all modes)
Timing response end to next CMD start (data transfer mode)
Command response timing (data transfer mode)
Host Command
Response
N
CR
cycles
CMD
Content
ST
EZ Z P
P S T
Content
CRC
EZ Z
******
CRC
Z
Response
Host Command
N
RC
cycles
CMD
Content
ST
EZ
Z S T
Content
CRC
EZ Z
******
CRC
Z
Host Command
Host Command
N
CC
cycles
CMD
Content
ST
EZ
Z S T
Content
CRC
EZ Z
******
CRC
Z
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