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參數(shù)資料
| 型號： | MC908QL4C |
| 廠商： | Motorola, Inc. |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 121/222頁 |
| 文件大?。?/td> | 2861K |
| 代理商： | MC908QL4C |
Reset and System Initialization
MC68HC908QL4 MC68HC908QL3 MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
121
(see
Figure 13-4
). An internal reset can be caused by an illegal address, illegal opcode, COP time out,
LVI, or POR (see
Figure 13-5
).
Figure 13-4. Internal Reset Timing
Figure 13-5. Sources of Internal Reset
13.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
At power on, the following events occur:
A POR pulse is generated.
The internal reset signal is asserted.
The SIM enables the oscillator to drive BUSCLKX4.
Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow
stabilization of the oscillator.
The POR bit of the SIM reset status register (SRSR) is set.
See
Figure 13-6
.
Table 13-2. Reset Recovery Timing
Reset Recovery Type
Actual Number of Cycles
POR/LVI
4163 (4096 + 64 + 3)
All others
67 (64 + 3)
IRST
RST
RST PULLEDLOWBYMCU
ADDRESS
32 CYCLES
32 CYCLES
VECTOR HIGH
BUSCLKX4
BUS
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC908QL4CDTE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:M68HC08 Microcontrollers |
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| MC908QL4DW | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC908QL4M | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
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