參數(shù)資料
        型號(hào): MC8641DVU1250JC
        廠商: FREESCALE SEMICONDUCTOR INC
        元件分類: 微控制器/微處理器
        英文描述: MICROPROCESSOR, CBGA1023
        封裝: 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
        文件頁數(shù): 33/140頁
        文件大?。?/td> 1484K
        代理商: MC8641DVU1250JC
        MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
        128
        Freescale Semiconductor
        System Design Information
        Table 73 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD,
        nominal OVDD, 105°C.
        20.8
        Configuration Pin Muxing
        The MPC8641 provides the user with power-on configuration options which can be set through the use of
        external pull-up or pull-down resistors of 4.7 k
        Ω on certain output pins (see customer visible configuration
        pins). These pins are generally used as output only pins in normal operation.
        While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
        while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
        and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
        with an on-chip gated resistor of approximately 20 k
        Ω. This value should permit the 4.7-kΩ resistor to pull
        the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
        for platform /system clocks after HRESET deassertion to ensure capture of the reset value). When the input
        receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
        minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
        been encoded such that a high voltage level puts the device into the default state and external resistors are
        needed only when non-default settings are required by the user.
        Careful board layout with stubless connections to these pull-down resistors coupled with the large value
        of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
        configured.
        The platform PLL ratio and e600 PLL ratio configuration pins are not equipped with these default pull-up
        devices.
        20.9
        JTAG Configuration Signals
        Correct operation of the JTAG interface requires configuration of a group of system control pins as
        demonstrated in Figure 68. Care must be taken to ensure that these pins are maintained at a valid deasserted
        state under normal operating conditions as most have asynchronous behavior and spurious assertion will
        give unpredictable results.
        Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
        IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture
        technology. The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary
        logic does not interfere with normal chip operation. While it is possible to force the TAP controller to the
        reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained
        Table 73. Impedance Characteristics
        Impedance
        DUART, Control,
        Configuration, Power
        Management
        PCI
        Express
        DDR DRAM
        Symbol
        Unit
        RN
        43 Target
        25 Target
        20 Target
        Z0
        W
        RP
        43 Target
        25 Target
        20 Target
        Z0
        W
        Note: Nominal supply voltages. See Table 1, Tj = 105°C.
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