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| 型號(hào)： | MC8641DHX1333JC |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 99/130頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU DUAL E600 CORE 1023FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.333GHz |
| 電壓： | 1.05V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCCBGA（33x33） |
| 包裝： | 托盤 |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
70
Freescale Semiconductor
PCI Express
14.1
DC Requirements for PCI Express SD
n_REF_CLK and
SD
n_REF_CLK
For more information, see Section 13.2, “SerDes Reference Clocks.”
14.2
AC Requirements for PCI Express SerDes Clocks
Table 48 lists AC requirements.
14.3
Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a +/– 300 ppm tolerance.
14.4
Physical Layer Specifications
The following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the Transport and Data Link layer please use the PCI
EXPRESS Base Specification. REV. 1.0a document.
14.4.1
Differential Transmitter (TX) Output
Table 49 defines the specifications for the differential output at all transmitters (TXs). The parameters are
specified at the component pins.
Table 48. SD
n_REF_CLK and SDn_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Notes
tREF
REFCLK cycle time
—
10
—
ns
—
tREFCJ
REFCLK cycle-to-cycle jitter. Difference in the period of any two
adjacent REFCLK cycles
—
100
ps
—
tREFPJ
Phase jitter. Deviation in edge location with respect to mean
edge location
–50
—
50
ps
—
Table 49. Differential Transmitter (TX) Output Specifications
Symbol
Parameter
Min
Nom
Max
Units
Comments
UI
Unit Interval
399.88
400
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not account for
Spread Spectrum Clock dictated variations. See Note
1.
VTX-DIFFp-p
Differential
Peak-to-Peak
Output Voltage
0.8—
1.2V
VTX-DIFFp-p = 2*|VTX-D+ – VTX-D-| See Note 2.
VTX-DE-RATIO
De- Emphasized
Differential
Output Voltage
(Ratio)
–3.0
–3.5
–4.0
dB
Ratio of the VTX-DIFFp-p of the second and following
bits after a transition divided by the VTX-DIFFp-p of the
first bit after a transition. See Note 2.
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