參數(shù)資料
型號: MC8640DVU1067NE
廠商: Freescale Semiconductor
文件頁數(shù): 73/130頁
文件大?。?/td> 0K
描述: IC MPU DUAL CORE E600 1023FCCBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.067GHz
電壓: 0.95V
安裝類型: 表面貼裝
封裝/外殼: 1023-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 1023-FCCBGA(33x33)
包裝: 托盤
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor
47
Local Bus
Figure 27 shows the local bus signals in PLL bypass mode.
Figure 27. Local Bus Signals (PLL Bypass Mode)
NOTE
In PLL bypass mode, LCLK[n] is the inverted version of the internal clock
with the delay of tLBKHKT. In this mode, signals are launched at the rising edge
of the internal clock and are captured at falling edge of the internal clock,
with the exception of the LGTA/LUPWAIT signal, which is captured at the
rising edge of the internal clock.
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKLOV2
LCLK[n]
Input Signals:
LAD[0:31]/LDP[0:3]
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
LALE
tLBIXKH1
Input Signal:
LGTA
Output (Address) Signal:
LAD[0:31]
tLBIVKH1
tLBIXKL2
tLBIVKL2
tLBKLOX1
tLBKLOZ2
tLBOTOT
Internal launch/capture clock
tLBKLOX2
tLBKLOV1
tLBKLOV3
tLBKLOZ1
tLBKHKT
tLBKLOV4
LUPWAIT
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