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參數(shù)資料
| 型號： | MC74VHC595D |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit Shift Register with Output Storage Register |
| 中文描述： | AHC/VHC SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 4/9頁 |
| 文件大?。?/td> | 206K |
| 代理商： | MC74VHC595D |
MC74VHC595
MOTOROLA
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
4
Typical @ 25
°
C, VCC = 5.0V
87
tPHZ
Cout
Three–State Output
RL = 1k
12.1
RL = 1k
Cin
Input Capacitance
4
10
10
pF
6
10
CPD
Power Dissipation Capacitance (Note 1.)
1 )
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR
)
= CPD VCC fin + ICC. CPD is used to determine the no–load dynamic
power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS
(Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)
Symbol
b l
Characteristic
i i
TA = 25
°
C
U i
Unit
Typ
Max
VOLP
VOLV
VIHD
VILD
Quiet Output Maximum Dynamic VOL
Quiet Output Minimum Dynamic VOL
Minimum High Level Dynamic Input Voltage
0.8
1.0
V
– 0.8
– 1.0
V
3.5
V
Maximum Low Level Dynamic Input Voltage
1.5
V
TIMING REQUIREMENTS
(Input tr = tf = 3.0ns)
TA = 25 C
3.5
3.0
tsu
5.0
Setup Time, SI to SCK
5.0
3.0
5.0
3.5
ns
Pulse Width, SCLR
5.0
3.0
5.0
Setup Time, SCLR to RCK
3.3
2.0
8.0
5.0
9.0
ns
Hold Time, SI to SCK
0
0
trec
3.3
Recovery Time, SCLR to SCK
5.0
5.0
5.0
3.0
ns
Pulse Width, SCK or RCK
5.0
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