參數(shù)資料
型號(hào): MC74HCT374ADWR2
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Octal 3-State Noninverting D Flip-Flop with LSTTL-Compatible Inputs
中文描述: HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
封裝: SOIC-20
文件頁(yè)數(shù): 4/8頁(yè)
文件大?。?/td> 185K
代理商: MC74HCT374ADWR2
MC74HCT374A
http://onsemi.com
4
NOTE: 1. Total Supply Current = ICC +
Σ
ICC.
NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
Current
Current
Vin= VCCor GND, Other Inputs
Vin = VCC or GND, Other In uts
5.5
2.9
2.4
mA
Semiconductor High–Speed CMOS Data Book (DL129/D).
Symbol
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
Parameter
30
25 C
85 C
24
125 C
20
MHz
(Figures 2 and 5)
tPLH,
Maximum Propagation Delay, Clock to Q
31
39
47
tPHZ
(Figures 2 and 5)
Maximum Propagation Delay, Output Enable to Q
tPZH
tTLH,
Maximum Output Transition Time, Any Output
12
15
18
(Output in High–Impedance State)
Maximum Three–State Output Capacitance
Typical @ 25
°
C, VCC = 5.0 V
65
CPD
Power Dissipation Capacitance (Per Flip–Flop)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
pF
TIMING REQUIREMENTS
(VCC = 5.0 V
±
10%, Input tr = tf = 6.0 ns)
Symbol
tsu
Minimum Setup Time, Data to Clock
Parameter
12
500
25 C
15
500
85 C
125 C
18
500
ns
(Figure 1)
Maximum Input Rise and Fall Times
(Figure 3)
Minimum Hold Time, Clock to Data
ns
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