參數(shù)資料
型號(hào): MC74HCT259ADTR2G
廠商: ON Semiconductor
文件頁數(shù): 2/9頁
文件大?。?/td> 0K
描述: 8-BIT ADDRESSABLE LATCH
標(biāo)準(zhǔn)包裝: 2,500
系列: 74HCT
邏輯類型: D 型,可尋址
電路: 1:8
輸出類型: 標(biāo)準(zhǔn)
電源電壓: 4.5 V ~ 5.5 V
獨(dú)立電路: 1
延遲時(shí)間 - 傳輸: 42ns
輸出電流高,低: 5.2mA,5.2mA
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 帶卷 (TR)
MC74HCT259A
http://onsemi.com
2
Figure 1. Logic Diagram
ADDRESS
INPUTS
A0
A1
A2
DATA IN
RESET
ENABLE
14
15
13
3
2
1
12
11
10
9
7
6
5
4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN 16 = VCC
PIN 8 = GND
NONINVERTING
OUTPUTS
LATCH SELECTION TABLE
Address Inputs
Latch Addressed
C
B
A
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to +7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air,
SOIC Package
TSSOP Package
500
450
mW
Tstg
Storage Temperature
65 to + 150
°C
VESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
>2000
>200
V
ILatchup Latchup Performance Above VDD and Below GND at
125°C (Note 3)
±100
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
1. Tested to EIA / JESD22A114A.
2. Tested to EIA / JESD22A115A.
3. Tested to EIA / JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
4.5
5.5
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+125
°C
tr, tf
Input Rise and Fall Time (Figure 2)
0
500
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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