參數(shù)資料
型號: MC74HC573ADWR2
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Octal 3-State Noninverting Transparent Latch
中文描述: HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20
封裝: SOIC-20
文件頁數(shù): 3/8頁
文件大小: 199K
代理商: MC74HC573ADWR2
MC74HC573A
http://onsemi.com
3
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: –10 mW/ C from 65 to 125 C
SOIC Package: –7 mW/ C from 65 to 125 C
TSSOP Package: –6.1 mW/
°
C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
Power Dissipation in Still Air,
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
±
20
±
35
±
75
mA
mA
mA
V
(Plastic DIP, TSSOP or SOIC Package)
V
V
Plastic DIP
SOIC Package
750
500
mW
260
C
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
(Figure 1)
500
0
VCC = 4.5 V
(DL129/D).
Guaranteed Limit
– 55 to
4.2
2.1
3.15
4.2
Voltage
6.0
Vout = 0.1 V or VCC – 0.1 V
|Iout|
20
μ
A
6.0
3.0
6.0
3.0
5.9
5.34
2.1
3.84
4.2
2.1
Voltage
|Iout|
20
μ
A
5.48
3.0
6.0
0.9
1.8
5.2
0.9
1.35
1 8
0.9
1.8
VOH
Minimum High–Level Output
Vin = VIH or VIL
|Iout|
20
μ
A
2.0
5.9
1.9
1.9
5.9
1.9
V
|Iout|
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
(Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
相關(guān)PDF資料
PDF描述
MC74HC573AN Octal 3-State Noninverting Transparent Latch
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MC74HC574ADW Octal 3-State Noninverting D Flip-Flop
MC74HC574ADWR2 Octal 3-State Noninverting D Flip-Flop
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