參數(shù)資料
型號(hào)： MC74HC4020ADT
廠商： ON SEMICONDUCTOR
元件分類： 通用總線功能
英文描述： 14-Stage Binary Ripple Counter
中文描述： HC/UH SERIES, ASYN NEGATIVE EDGE TRIGGERED 14-BIT UP BINARY COUNTER, PDSO16
封裝： TSSOP-16
文件頁(yè)數(shù)： 2/8頁(yè)
文件大?。?/td> 167K
代理商： MC74HC4020ADT
MC74HC4020A
http://onsemi.com
2
Functional operation should be restricted to the Recommended Operating Conditions.
Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
– 0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
±
25
V
DC Output Current, per Pin
mA
SOIC Package
500
Plastic DIP, SOIC or TSSOP Package
Lead Temperature, 1 mm from Case for 10 Seconds
260
C
Input Rise/Fall Time
(Figure 1)
500
C
VCC = 2.0 V
VCC = 4.5 V
0
0
0
DC CHARACTERISTICS
(Voltages Referenced to GND)
VCC
V
Guaranteed Limit
Symbol
Parameter
Condition
–55 to 25
°
C
≤
85
°
C
≤
125
°
C
Unit
VIH
Minimum High–Level Input
Voltage
Vout = 0.1V or VCC –0.1V
|Iout|
≤
20
μ
A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
VIL
Maximum Low–Level Input
Voltage
Vout = 0.1V or VCC – 0.1V
|Iout|
≤
20
μ
A
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
VOH
Minimum High–Level Output
Voltage
Vin = VIH or VIL
|Iout|
≤
20
μ
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin =VIH or VIL
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOL
Maximum Low–Level Output
Voltage
Vin = VIH or VIL
|Iout|
≤
20
μ
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL
|Iout|
≤
2.4mA
|Iout|
≤
4.0mA
|Iout|
≤
5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
(Vin or Vout)
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
VCC.
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