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參數(shù)資料
| 型號： | MC74HC175N |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad D Flip-Flop with Common Clock and Reset |
| 中文描述： | 四D觸發(fā)器與普通時鐘和復(fù)位拖鞋 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 200K |
| 代理商： | MC74HC175N |
MC54/74HC175
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
(Figures 1 and 4)
4.5
30
20
6.0
26
24
38
tPHL
Maximum Propagation Delay, Reset to Q or Q
2.0
125
155
33
190
ns
tTHL
(Figures 1 and 4)
4.5
15
22
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
19
CPD
Power Dissipation Capacitance (Per Flip–Flop)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
35
pF
Symbol
Parameter
V
25 C
125 C
tsu
Minimum Setup Time, Data to Clock
2.0
100
85 C
125
150
Unit
ns
(Figure 3)
4.5
3
(Figure 2)
4.5
6.0
20
17
3
30
26
3
tw
Minimum Pulse Width, Clock
2.0
6.0
80
14
100
25
21
120
20
ns
Minimum Pulse Width, Reset
(Figure 2)
2.0
4.5
80
16
100
17
120
24
ns
(Figure 1)
4.5
6.0
500
400
500
400
20
500
400
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