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參數(shù)資料
| 型號(hào)： | MC74HC175AN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Quad D Flip=Flop with Common Clck and Reset |
| 中文描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 1/7頁(yè) |
| 文件大?。?/td> | 200K |
| 代理商： | MC74HC175AN |
SEMICONDUCTOR TECHNICAL DATA
1
REV 6
Motorola, Inc. 1995
10/95
! "
High–Performance Silicon–Gate CMOS
The MC54/74HC175 is identical in pinout to the LS175. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
This device consists of four D flip–flops with common Reset and Clock
inputs, and separate D inputs. Reset (active–low) is asynchronous and
occurs when a low level is applied to the Reset input. Information at a D input
is transferred to the corresponding Q output on the next positive going edge
of the Clock input.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity 166 FETs or 41.5 Equivalent Gates
LOGIC DIAGRAM
PIN 16 = VCC
PIN 8 = GND
9
4
5
12
13
CLOCK
D0
D1
D2
D3
RESET
1
DATA
INPUTS
2
3
7
6
10
11
15
14
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
INVERTING
AND
NONINVERTING
OUTPUTS
PIN ASSIGNMENT
FUNCTION TABLE
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
D2
D3
Q3
Q3
VCC
CLOCK
Q2
Q2
D0
Q0
Q0
RESET
GND
Q1
Q1
D1
Inputs
Clock
Outputs
Q
Reset
D
Q
L
H
H
H
X
X
H
L
X
L
H
L
H
L
H
L
No Change
D SUFFIX
SOIC PACKAGE
CASE 751B–05
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ORDERING INFORMATION
MC54HCXXXJ
MC74HCXXXN
MC74HCXXXD
Ceramic
Plastic
SOIC
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
1
16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC74HC175D | Quad D Flip-Flop with Common Clock and Reset |
| MC74HC175N | Quad D Flip-Flop with Common Clock and Reset |
| MC54-74HC240A | Octal 3-State Inverting Buffer/Line Driver/Line Receiver |
| MC74HC240ADTR2 | Octal 3-State Inverting Buffer/Line Driver/Line Receiver |
| MC74HC240A | Octal 3-State Inverting Buffer/Line Driver/Line Receiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74HC175ANG | 功能描述:觸發(fā)器 2-6V CMOS Quad D-Type Clock Reset RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時(shí)間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC74HC175D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74HC175DR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74HC175DTR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC74HC175FEL | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述: |
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