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參數(shù)資料
| 型號： | MC74AC109DR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual JK Positive Edge−Triggered Flip−Flop |
| 中文描述： | AC SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 242K |
| 代理商： | MC74AC109DR2 |
MC74AC109, MC74ACT109
http://onsemi.com
5
DC CHARACTERISTICS (continued)
Symbol
Conditions
Unit
74ACT
74ACT
(V)
Parameter
T
A
=
40
°
C to
+85
°
C
T
A
= +25
°
C
V
CC
Guaranteed Limits
Typ
V
OL
Maximum Low Level
Output Voltage
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
V
I
OUT
= 50
μ
A
*V
IN
= V
IL
or V
IH
4.5
5.5
0.36
0.36
0.44
0.44
V
I
OL
24 mA
24 mA
I
IN
Maximum Input
Leakage Current
5.5
±
0.1
±
1.0
μ
A
V
I
= V
CC
, GND
Δ
I
CCT
Additional Max. I
CC
/Input
5.5
0.6
1.5
mA
V
I
= V
CC
2.1 V
I
OLD
Minimum Dynamic
Output Current
5.5
75
mA
V
OLD
= 1.65 V Max
I
OHD
5.5
75
mA
V
OHD
= 3.85 V Min
I
CC
Maximum Quiescent
Supply Current
5.5
4.0
40
μ
A
V
IN
= V
CC
or GND
*All outputs loaded; thresholds on input associated with output under test.
Maximum test duration 2.0 ms, one output loaded at a time.
AC CHARACTERISTICS
(For Figures and Waveforms
See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
Symbol
Parameter
V
CC
*
(V)
74ACT
74ACT
Unit
Fig.
No.
T
A
= +25
°
C
C
L
= 50 pF
T
A
=
40
°
C
to +85
°
C
C
L
= 50 pF
Min
Typ
Max
Min
Max
f
max
Maximum Clock
Frequency
5.0
145
125
MHz
3
3
t
PLH
Propagation Delay
CP
n
to Q
n
or Q
n
Propagation Delay
CP
n
to Q
n
or Q
n
Propagation Delay
C
Dn
or S
Dn
to Q
n
or Q
n
Propagation Delay
C
Dn
or S
Dn
to Q
n
or Q
n
5.0
4.0
11.0
3.5
13.0
ns
3
6
t
PHL
5.0
3.0
10.0
2.5
11.5
ns
3
6
t
PLH
5.0
2.5
9.5
2.0
10.5
ns
3
6
t
PHL
5.0
2.5
10.0
2.0
11.5
ns
3
6
*Voltage Range 5.0 V is 5.0 V
±
0.5 V.
AC OPERATING REQUIREMENTS
Symbol
Parameter
V
CC
*
(V)
74ACT
74ACT
Unit
Fig.
No.
T
A
= +25
°
C
C
L
= 50 pF
T
A
=
40
°
C
to +85
°
C
C
L
= 50 pF
Typ
Guaranteed Minimum
t
s
Set
up Time, HIGH or LOW
J
n
or K
n
to CP
n
Hold Time, HIGH or LOW
J
n
or K
n
to CP
n
Pulse Width
CP
n or
C
Dn
or S
Dn
5.0
2.0
2.5
ns
3
9
t
h
5.0
2.0
2.0
ns
3
9
t
w
5.0
5.0
6.0
ns
3
6
*Voltage Range 5.0 V is 5.0 V
±
0.5 V.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC74AC109DT | Dual JK Positive Edge−Triggered Flip−Flop |
| MC74AC109DTR2 | Dual JK Positive Edge−Triggered Flip−Flop |
| MC74AC109M | Dual JK Positive Edge−Triggered Flip−Flop |
| MC74AC109MEL | Dual JK Positive Edge−Triggered Flip−Flop |
| MC74ACT109DR2 | Dual JK Positive Edge−Triggered Flip−Flop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC74AC109DT | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop |
| MC74AC109DTR2 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop |
| MC74AC109M | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop |
| MC74AC109MEL | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Dual JK Positive Edge−Triggered Flip−Flop |
| MC74AC109N | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:DUAL JK POSITIVE EDGE-TRIGGERED FLIP-FLOP |
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