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參數(shù)資料
| 型號： | MC74 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 溫度/濕度傳感器 |
| 英文描述： | Serial Digital Temperature Sensor |
| 中文描述： | 串行數(shù)字溫度傳感器 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 122K |
| 代理商： | MC74 |
MC74
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
(VDD = 3.3 V or 5.0V (5), –40
°
C
≤
TA
≤
125
°
C, unless otherwise noted.)
Symbol
Characteristic
Min
Typ
Max
Unit
Power Supply
VPOR
Power–On Reset Threshold
(VDD Falling Edge or Rising Edge)
1.2
—
2.2
V
IDD
Operating Current
(VDD = 5.5V, Serial Port Inactive) (1)
—
200
350
A
IDD–STANDBY
Standby Supply Current
(VDD = 3.3 V, Serial Port Inactive) (4)
—
5.0
10
A
Temperature–to–Bits Converter
TERR
Temperature Accuracy MC74A
+25
°
C
≤
TA
≤
+85
°
C
0
°
C
≤
TA
≤
+125
°
C
–40
°
C
≤
TA
≤
0
°
C
Conversion Rate (2)
–2.0
–3.0
—
—
—
±
2.0
+2.0
+3.0
—
°
C
CR
4.0
8.0
—
sa/sec
Serial Port Interface
VIH
VIL
VOL
Logic Input High
0.8 x VDD
—
—
—
V
Logic Input Low
—
0.2 x VDD
V
SDA Output Low
IOL = 3 mA (3)
IOL = 6 mA (3)
Input Capacitance SDA, SCL
—
—
—
—
0.4
0.6
V
CIN
ILEAK
1. Operating current is an average value integrated over multiple conversion cycles. Transient current may exceed this specification.
2. Maximum guaranteed conversion time after Power–On RESET (POR to DATA_RDY) is 250 msec.
3. Output current should be minimized for best temperature accuracy. Power dissipation within the MC74 will cause self–heating and
temperature drift error.
4. SDA and SCL must be connected to VDD or GND.
5. VDD = 3.3V for MC74A5–33SNTR. VDD = 5.0V for MC74A5–50T. All part types of the MC74 will operate properly over the wider power supply
range of 2.7V to 5.5V. Each part type is tested and specified for rated accuracy at its nominal supply voltage. As VDD varies from the nominal
value, accuracy will degrade 1
°
C/V of VDD change.
—
5.0
—
pF
I/O Leakage
–1.0
0.1
1.0
A
SERIAL PORT AC TIMING
(VDD = 3.3 V or 5.0V, –40
°
C
≤
(TA = TJ)
≤
125
°
C; CL = 80 pF unless otherwise noted.)
Symbol
Characteristic
Min
Typ
Max
Unit
fSMB
tLOW
tHIGH
tR
tF
tSU(START)
SMBus Clock Frequency
10
—
100
kHz
Low Clock Period (10% to 10%)
4.7
—
—
sec
High Clock Period (90% to 90%)
4.0
—
—
sec
SMBus Rise Time (10% to 90%)
—
—
1,000
nsec
SMBus Fall Time (90% to 10%)
—
—
300
nsec
Start Condition Setup Time (90% SCL to 10% SDA)
(for Repeated Start Condition)
4.0
—
—
sec
tH(START)
tSU–DATA
tH–DATA
tSU(STOP)
tIDLE
tPOR
Start Condition Hold Time
4.0
—
—
sec
Data in Setup Time
1,000
—
—
nsec
Data in Hold Time
1,250
—
—
nsec
Stop Condition Setup Time
4.0
—
—
sec
Bus Free Time Prior to New Transition
4.7
—
—
sec
Power–On Reset Delay (VDD
≥
VPOR (Rising Edge))
—
500
—
sec
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