參數(shù)資料
型號(hào)： MC7455ARX933LG
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： RISC Microprocessor Hardware Specifications
中文描述： RISC微處理器硬件規(guī)格
文件頁(yè)數(shù)： 14/64頁(yè)
文件大?。?/td> 1127K
代理商： MC7455ARX933LG
MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1
14
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 7
provides the power consumption for the MPC7455.
Input leakage current,
V
in
= GV
DD
/OV
DD
+ 0.3 V
—
I
in
—
30
μA
2, 3
High impedance (off-state) leakage
current, V
in
= GV
DD
/OV
DD
+ 0.3 V
—
I
TSI
—
30
μA
2, 3, 5
Output high voltage, I
OH
= –5 mA
1.5
V
OH
GV
DD
– 0.45
—
V
6
1.8
V
OH
OV
DD
/GV
DD
– 0.45
—
V
2.5
V
OH
1.7
—
V
Output low voltage, I
OL
= 5 mA
1.5
V
OL
—
0.45
V
6
1.8
V
OL
—
0.45
V
2.5
V
OL
—
0.7
V
Capacitance,
V
in
= 0 V,
f = 1 MHz
L3 interface
—
C
in
—
9.5
pF
4
All other inputs
—
8.0
pF
4
Notes
:
1. Nominal voltages; see
Table 4
for recommended operating conditions.
2. For processor bus signals, the reference is OV
DD
while GV
DD
is the reference for the L3 bus signals.
3. Excludes test signals and IEEE 1149.1 boundary scan (JTAG) signals.
4. Capacitance is periodically sampled rather than 100% tested.
5. The leakage is measured for nominal OV
DD
/GV
DD
and V
DD
, or both OV
DD
/GV
DD
and V
DD
must vary in the same
direction (for example, both OV
DD
and V
DD
vary by either +5% or –5%).
6. Applicable to L3 bus interface only.
Table 7. Power Consumption for MPC7455
Processor (CPU) Frequency
Unit
Notes
733 MHz
867 MHz
933 MHz
1 GHz
Full-Power Mode
Typical
11.5
12.9
13.6
15.0
W
1, 3
Maximum
17.0
19.0
20.0
22.0
W
1, 2
Doze Mode
Typical
—
—
—
—
W
4
Nap Mode
Typical
8.0
8.0
8.0
8.0
W
1, 3
Sleep Mode
Table 6. DC Electrical Specifications (continued)
At recommended operating conditions. See
Table 4
.
Characteristic
Nominal
Bus
Voltage
1
Symbol
Min
Max
Unit
Notes
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