參數(shù)資料
型號(hào)： MC68VZ328
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： i.MX Integrated Portable System Processor
中文描述： i.MX處理器集成的便攜式系統(tǒng)
文件頁(yè)數(shù)： 65/96頁(yè)
文件大?。?/td> 1495K
代理商： MC68VZ328
Specifications
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
65
3.15.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card response
to the host command starts after exactly N
ID
clock cycles. For the card address assignment, SET_RCA is also
processed in the open-drain mode. The minimum delay between the host command and card response is NCR
clock cycles as illustrated in Figure 48. The symbols for Figure 48 through Figure 52 are defined in Table 30.
Figure 48. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in Figure 49 on
page 66, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a period of
two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the responding card.
The other two diagrams show the separating periods N
RC
and N
CC
.
Table 30. State Signal Parameters for Figure 48 through Figure 52
Card Active
Host Active
Symbol
Definition
Symbol
Definition
Z
High impedance state
S
Start bit (0)
D
Data bits
T
Transmitter bit
(Host = 1, Card = 0)
*
Repetition
P
One-cycle pull-up (1)
CRC
Cyclic redundancy check bits (7 bits)
E
End bit (1)
SET_RCA Timing
Identification Timing
Host Command
CID/OCR
N
ID
cycles
CMD
Content
ST
EZ
Z S T
Content
Z Z
******
CRC
Z
Host Command
CID/OCR
N
CR
cycles
CMD
Content
ST
EZ
Z S T
Content
Z Z
******
CRC
Z
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MC68VZ328CPV 制造商:FRESCL 功能描述:
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