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MOTOROLA
iv
MC68HC11PH8
TABLE OF CONTENTS
Paragraph
Number
Page
Number
Title
5.7
Status ags and interrupts.....................................................................................5-13
5.7.1
Receiver ags ..................................................................................................5-13
5.8
SCI2 ......................................................................................................................5-15
5.8.1
S2BDH, S2BDL — SCI2 baud rate control registers .......................................5-15
5.8.2
S2CR1 — SCI2 control register 1....................................................................5-16
5.8.3
S2CR2 — SCI2 control register 2....................................................................5-16
5.8.4
S2SR1 — SCI2 status register 1 .....................................................................5-16
5.8.5
S2SR2 — SCI2 status register 2 .....................................................................5-17
5.8.6
S2DRH, S2DRL — SCI2 data high/low registers ............................................5-17
6
MOTOROLA INTERCONNECT BUS (MI BUS)
6.1
Push-pull sequence ...............................................................................................6-2
6.1.1
The push eld ..................................................................................................6-2
6.1.2
The pull eld ....................................................................................................6-3
6.2
Biphase coding ......................................................................................................6-3
6.3
Message validation................................................................................................6-4
6.3.1
Controller detected errors ................................................................................6-4
6.3.2
MCU detected errors .......................................................................................6-4
6.4
Interfacing to MI BUS ............................................................................................6-6
6.5
MI BUS clock rate ..................................................................................................6-7
6.6
SCI2/MI BUS registers ..........................................................................................6-7
6.6.1
INIT2 — EEPROM mapping and MI BUS delay register .................................6-8
6.6.2
S2BDH, S2BDL — MI BUS clock rate control registers...................................6-9
6.6.3
S2CR1 — MI BUS control register 1 ...............................................................6-9
6.6.4
S2CR2 — MI BUS control register 2 ...............................................................6-10
6.6.5
S2SR1 — MI BUS status register 1 .................................................................6-11
6.6.6
S2SR2 — MI BUS2 status register 2 ...............................................................6-12
6.6.7
S2DRL — MI BUS2 data register ....................................................................6-12
7
SERIAL PERIPHERAL INTERFACE
7.1
Functional description ...........................................................................................7-1
7.2
SPI transfer formats...............................................................................................7-2
7.2.1
Clock phase and polarity controls ....................................................................7-3
7.3
SPI signals ............................................................................................................7-3
7.3.1
Master in slave out...........................................................................................7-4
7.3.2
Master out slave in...........................................................................................7-4
7.3.3
Serial clock ......................................................................................................7-4
7.3.4
Slave select......................................................................................................7-4
7.4
SPI system errors ..................................................................................................7-5
TPG
10