參數(shù)資料
型號: MC68MH360VR33L
廠商: Freescale Semiconductor
文件頁數(shù): 47/158頁
文件大?。?/td> 0K
描述: IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 44
系列: M683xx
處理器類型: M683xx 32-位
速度: 33MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤
QMC Supplement
Figure C-3. IDL and SCP Connections between the QUICC32 and the U Interface
As with the S/T interface example, the U interface must be congured in slave mode with
the DCL and FSC signals provided to both the QUICC32 and the U interface.
In slave mode, the FSX and FSR signals of the MC145572 must be connected together.
There are no DREQ/DGRANT signals on the U interface.
C.3 Data Clock (DCL) and Frame Sync (FSC)
Generation
The main consideration when connecting multiple interfaces to the same physical medium
is the clock and frame sync generation.
As stated earlier, the QUICC32 does not provide DCL and FSC signals. The U or S/T
interface could be congured in master mode on the IDL bus and generate both DCL and
FSC synchronized to the line-interface signal.
To have all the B- and D channels of a multi-interface system synchronized on the same
TDM bus, only one S/T or U interface should be congured as master to provide common
DCL and FSC signals to the QUICC32 and all other interfaces.
ISDN
U Chip
MC145572
QUICC32
DCL
DIN
DOUT
FSX
FSR
IRQ
SCPEN
L1CLKx
L1TXDx
L1RXDx
L1SYNC
IRQ
GPI/O
SPICLK
SPITX
SPIRX
SCPCLK
SCPRX
SCPTX
Line
Interface
Pullup resistors on SCPEN and IRQ pins
are not represented.
*
NT/LT
M/S
GND
VCC
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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