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| 型號(hào)： | MC68LC302PU20VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁(yè)數(shù)： | 109/128頁(yè) |
| 文件大?。?/td> | 641K |
| 代理商： | MC68LC302PU20VCT |
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Applications
6-2
MC68EN302 REFERENCE MANUAL
MOTOROLA
and the pin muxing that is used in the current MC68EN302 application.
Example: Write $5400 to MBC (MFC = 5, PPE = 1).
7. IER - The interrupt extension register replaces the MOD, ET7, ET6 and ET1 bits in the
302 GIMR.
The user MUST assure that the corresponding bits in the GIMR of the
internal 302 are all written as zeros for proper functionality of the MC68EN302. The
IER is reset to $0000 which configures the interrupt input pins as IPL2–IPL0 and sets
the module bus controller interrupt to level 5.
8. CSER0–CSER3. The MC68EN302 extends the functionality of that provided by the
internal 302 core chip selects through the programming of this register. Additional
functionality includes 8-bit bus operation as well as parity checking and generation.
9. PCSR - This register controls parity operation on the MC68EN302. Also, bits 9-8 show
the result of parity on the current DRAM bank.
10. DRAM controller initialization. Assume bank 0 is to be used, parity enabled, 0 wait
states.
DRAM Configuration Register (DCR) = $0501 (Enable refresh and parity in bank 0,
allow supervisor or user access)
DRAM Refresh Register (DRFRSH) = $0000 (Refresh every 4096 system clocks)
DRAM Base Address Registers
DBA0 = desired DRAM base address and size, bit 0 = 1
DBA1 = $0000 (reset value)
To ensure correct parity, write $0000 to each memory location used before running
other code.
11. Ethernet Controller Initialization. In this example the Ethernet Controller is initialized to
perform internal loopback of one frame. The received frame buffer will be 4 bytes
longer than the transmit buffer due to the CRC being appended by hardware.
ECNTRL = $0001 (Release RESET to the Ethernet Controller)
EDMA = $000B
WMRK = 01 (16 bytes)
BLIM = 011 (max DMA burst length of 8 bus transactions (16 bytes of data))
EMRBLR = $0600 (1536 bytes, this allows receiving a max size frame into a single
buffer).
IVEC = $0140
VG = 1 (bit 1–bit 0 of the interrupt vector will be modified).
INV7–INV0 = 40
INTR_MASK = $07BC (all interrupts enabled except BackOffDone, TransmitBuffer
and ReceiveBuffer).
ECNFIG = $0001 (enable internal loopback).
ETHER_TEST = $0000
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