- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄45248 > MC68LC302PU16V (MOTOROLA INC) 32-BIT, 16.67 MHz, RISC MICROCONTROLLER, PQFP100 PDF資料下載
參數(shù)資料
| 型號： | MC68LC302PU16V |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 16.67 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 119/182頁 |
| 文件大小： | 618K |
| 代理商： | MC68LC302PU16V |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁當前第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁
System Integration Block (SIB)
3-4
MC68LC302 REFERENCE MANUAL
MOTOROLA
BG, regardless of the M68000 core RMC. If an IMP chip select is used then the
DTACK generator will insert wait states on the read cycle only.
1 = The IMP uses the internal RMC to negate AS and CS at the end of the read portion
of the RMC cycle and reasserts AS and CS at the beginning of the write portion.
BG will not be asserted until the end of the write portion. If an IMP chip select is
used, the DTACK generator will insert wait states on both the read and write portion
of the cycles.
The assertion of the internal RMC by the M68000 core is seen by the arbiter and will pre-
vent the arbiter from issuing bus grants until the completion of M68000-initiated locked
read-modify-write activity. After system reset, this bit defaults to zero.
EMWS—External Master Wait State (EMWS) (VALID only in Disable CPU Mode)
When EMWS is set and an external master is using the chip-select logic for DTACK gen-
eration or is synchronously reading from the internal peripherals (SAM = 1), one additional
wait state will be inserted in every memory cycle to external memory, peripherals, and al-
so, in every cycle to internal memory and peripherals. When EMWS is cleared, all syn-
chronous internal accesses will be with zero wait states and the chip-select logic will
generate DTACK after the exact programmed number of wait states. The chip-select lines
are asserted slightly earlier for internal master memory cycles than for an external master.
EMWS should be set whenever these timing differences will necessitate an additional wait
state for external masters. After system reset, this bit defaults to zero.
ADCE—Address Decode Conflict Enable
0 = an internal BERR is not asserted by a conflict in the chip-select logic when two or
more chip-select lines are programmed to overlap the same area.
1 = an internal BERR is asserted by a conflict in the chip-select logic when two or more
chip-select lines are programmed to overlap the same area.
BCLM—Bus Clear Mask
0 = The arbiter does not use the M68000 core internal IPEND signal to assert the in-
ternal bus clear signals.
1 = The arbiter uses the M68000 core internal IPEND signal to assert the internal bus
clear signals.
SAM—Synchronous Access Mode (Valid only in Disable CPU Mode)
This bit controls how external masters may access the IMP peripheral area. This bit is not
relevant for applications that do not have external bus masters that access the IMP. In ap-
plications such as disable CPU mode, in which the M68000 core is not operating, the user
should note that SAM may be changed by an external master on the first access of the
IMP, but that first write access must be asynchronous with three wait states. (If DTACK is
used to terminate bus cycles, this change need not influence hardware.)
0 = Asynchronous accesses. All accesses to the IMP internal RAM and registers (in-
cluding BAR and SCR) by an external master are asynchronous to the IMP clock.
Read and write accesses are with three wait states, and DTACK is asserted by the
IMP assuming three wait-state accesses. This is the default value.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68LC302RC25B | 32-BIT, 25 MHz, RISC MICROCONTROLLER, CPGA132 |
| MC68LC302CPU16B | 32-BIT, 16.67 MHz, RISC MICROCONTROLLER, PQFP100 |
| MC68LC302PU16VB | 32-BIT, 16.67 MHz, RISC MICROCONTROLLER, PQFP100 |
| MC68LC302CPU20VB | 32-BIT, 20 MHz, RISC MICROCONTROLLER, PQFP100 |
| MC68LC302PU25B | 32-BIT, 25 MHz, RISC MICROCONTROLLER, PQFP100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68LC302PU16VCT | 功能描述:IC MPU NETWORK 16MHZ 100-LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| MC68LC302PU20CT | 功能描述:微處理器 - MPU 20MHz 2MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68LC302PU20VCT | 功能描述:IC MPU NETWORK 20MHZ 100-LQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M683xx 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25） 包裝:托盤 |
| MC68LC302PU25CT | 功能描述:微處理器 - MPU 25MHz 2.5MIPS RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68LK332ACAG16 | 功能描述:32位微控制器 - MCU 32BIT MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。