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參數(shù)資料
型號(hào): MC68L11D0CFBE2
廠商: Freescale Semiconductor
文件頁數(shù): 34/124頁
文件大?。?/td> 0K
描述: IC MCU 8BIT LV 192RAM 44-QFP
標(biāo)準(zhǔn)包裝: 96
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 2MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器類型: ROMless
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-QFP
包裝: 托盤
PIN DESCRIPTIONS
TECHNICAL DATA
2-5
sensitive, it can be connected to a multiple-source wired-OR network with an external
pullup resistor to VDD. XIRQ is often used as a power loss detect interrupt.
Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ must be config-
ured for level-sensitive operation if there is more than one source of IRQ interrupt),
each source must drive the interrupt input with an open-drain type of driver to avoid
contention between outputs. There should be a single pullup resistor near the MCU
interrupt input pin (typically 4.7 k
). There must also be an interlock mechanism at
each interrupt source so that the source holds the interrupt line low until the MCU rec-
ognizes and acknowledges the interrupt request. If one or more interrupt sources are
still pending after the MCU services a request, the interrupt line will still be held low
and the MCU will be interrupted again as soon as the interrupt mask bit in the MCU is
cleared (normally upon return from an interrupt). Refer to SECTION 5 RESETS AND
2.7 MODA and MODB (MODA/LIR,and MODB/VSTBY)
During reset, MODA and MODB select one of the four operating modes. Refer to SEC-
After the operating mode has been selected, the LIR pin provides an open-drain output
to indicate that execution of an instruction has begun. A series of E-clock cycles occurs
during execution of each instruction. The LIR signal goes low during the first E-clock
cycle of each instruction (opcode fetch). This output is provided for assistance in pro-
gram debugging.
The VSTBY pin is used to input RAM standby power. When the voltage on this pin is
more than one MOS threshold (about 0.7 volts) above the VDD voltage, the internal
192-byte RAM and part of the reset logic are powered from this signal rather than the
VDD input. This allows RAM contents to be retained without VDD power applied to the
MCU. Reset must be driven low before VDD is removed and must remain low until VDD
has been restored to a valid level.
2.8 PD6/AS
This pin performs either of two separate functions, depending on the operating mode.
In single-chip and bootstrap modes, the pin functions as input/output port D bit 6. In
the expanded multiplexed and test modes, it provides an address strobe (AS) function.
The AS can demultiplex the address and data signals at port C. Refer to SECTION 4
OPERATING MODES AND ON-CHIP MEMORY for further information.
2.9 PD7/R/W
This pin provides two separate functions, depending on the operating mode. In single-
chip and bootstrap modes, PD7/R/W acts as input/output port D bit 7. Refer to SEC-
TION 6 PARALLEL I/O for further information.
In expanded multiplexed and test modes, PD7/R/W performs a read/write function.
PD7/R/W controls the direction of transfers on the external data bus. A high on this pin
indicates that a read cycle is in progress.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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