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SPI Registers
MC68HC05C8A MC68HCL05C8A MC68HSC05C8A Data Sheet, Rev. 5.1
Freescale Semiconductor
63
10.5.1 Serial Peripheral Control Register
SPIE — Serial Peripheral Interrupt Enable Bit
0 = SPIF interrupts disabled
1 = SPI interrupt is enabled
SPE — Serial Peripheral System Enable Bit
0 = SPI system off
1 = SPI system on
MSTR — Master Mode Select Bit
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being transferred, a steady state low value is
produced at the SCK pin of the master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit also is used in conjunction with the clock phase control bit to produce the desired clock-data
relationship between master and slave. See Figure 10-1.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPOL bit can be thought of as simply inserting an inverter in series with the
SCK line. The CPHA bit selects one of two fundamentally different clocking protocols. When CPHA =
0, the shift clock is the OR of SCK with SS. As soon as SS goes low, the transaction begins and the
first edge on SCK invokes the first data sample. When CPHA = 1, the SS pin may be thought of as a
simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Select Bits
These two bits select one of four baud rates to be used as SCK if the device is a master; however, they
have no effect in the slave mode. See Table 10-1.
Address: $000A
Bit 7
654321
Bit 0
Read:
SPIE
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
Write:
Reset
000000
U
= Unimplemented
U = Unaffected
Figure 10-4. SPI Control Register (SPCR)
Table 10-1. Serial Peripheral Rate Selection
SPR1
SPR0
Bus Clock Divided By
00
2
01
4
10
16
11
32
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