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參數(shù)資料
| 型號(hào)： | MC68HLC908QY2CDT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 2 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁(yè)數(shù)： | 177/186頁(yè) |
| 文件大小： | 2765K |
| 代理商： | MC68HLC908QY2CDT |
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Low-Voltage Inhibit (LVI)
Data Sheet
MC68HLC908QY/QT Family — Rev. 2
90
Low-Voltage Inhibit (LVI)
MOTOROLA
The LVI is enabled out of reset. The LVI module contains a bandgap reference
circuit and comparator. Clearing the LVI power disable bit (LVIPWRD) enables the
LVI to monitor VDD voltage. Clearing the LVI reset disable bit (LVIRSTD) enables
the LVI module to generate a reset when VDD falls below a voltage, VTRIPF or
VDTRIPF. Setting the LVI enable in stop mode bit (LVISTOP) enables the LVI to
operate in stop mode. Setting the LVD or LVR trip point bit (LVDLVR) selects the
LVD trip point voltage. The actual trip thresholds are specified in 16.5 DC
Electrical Characteristics. Either trip level can be used as a detect or reset.
NOTE:
After a power-on reset, the LVI’s default mode of operation is LVR trip voltage. If a
higher trip voltage is desired, the user must set the LVDLVR bit to raise the trip
point to the LVD voltage.
If the user requires the higher trip voltage and sets the LVDLVR bit after power-on
reset while the VDD supply is not above the VTRIPR for LVD mode, the
microcontroller unit (MCU) will immediately go into reset. The next time the LVI
releases the reset, the supply will be above the VTRIPR for LVD mode.
Once an LVI reset occurs, the MCU remains in reset until VDD rises above a
Integration Module (SIM) for the reset recovery sequence.
The output of the comparator controls the state of the LVIOUT flag in the LVI status
register (LVISR) and can be used for polling LVI operation when the LVI reset is
disabled.
10.3.1 Polled LVI Operation
In applications that can operate at VDD levels below the VTRIPF level, software can
monitor VDD by polling the LVIOUT bit. In the configuration register, the LVIPWRD
bit must be cleared to enable the LVI module, and the LVIRSTD bit must be set to
disable LVI resets.
10.3.2 Forced Reset Operation
In applications that require VDD to remain above the VTRIPF level, enabling LVI
resets allows the LVI module to reset the MCU when VDD falls below the VTRIPF
level. In the configuration register, the LVIPWRD and LVIRSTD bits must be
cleared to enable the LVI module and to enable LVI resets.
10.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain
a reset condition until VDD rises above the rising trip point voltage, VTRIPR. This
prevents a condition in which the MCU is continually entering and exiting reset if
VDD is approximately equal to VTRIPF. VTRIPR is greater than VTRIPF by the
hysteresis voltage, VHYS.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HLC908QY2CDW | 制造商:Rochester Electronics LLC 功能描述:LOW V-1.5K FLASH W/ADC - Bulk |
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| MC68HLC908QY4CP | 制造商:Rochester Electronics LLC 功能描述:LOW V-4K FLASH W/ADC - Bulk |
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