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Features
MC68HC908GT16 MC68HC908GT8 Data Sheet, Rev. 3
Freescale Semiconductor
221
18.2 Features
Features of the TIM include:
Two input capture/output compare channels:
–
Rising-edge, falling-edge, or any-edge input capture trigger
–
Set, clear, or toggle output compare action
Buffered and unbuffered pulse-width-modulation (PWM) signal generation
Programmable TIM clock input with 7-frequency internal bus clock prescaler selection
Free-running or modulo up-count operation
Toggle any channel pin on overflow
TIM counter stop and reset bits
18.3 Pin Name Conventions
The text that follows describes both timers, TIM1 and TIM2. The TIM input/output (I/O) pin names are
T[1,2]CH0 (timer channel 0) and T[1,2]CH1 (timer channel 1), where “1” is used to indicate TIM1 and “2”
is used to indicate TIM2. The two TIMs share four I/O pins with four port D I/O port pins.
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TCH0 may refer generically to
T1CH0 and T2CH0, and TCH1 may refer to T1CH1 and T2CH1.
18.4 Functional Description
Figure 18-1
shows the structure of the TIM. The central component of the TIM is the 16-bit TIM counter
that can operate as a free-running counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM counter modulo registers,
TMODH:TMODL, control the modulo value of the TIM counter. Software can read the TIM counter value
at any time without affecting the counting sequence.
The two TIM channels (per timer) are programmable independently as input capture or output compare
channels. If a channel is configured as input capture, then an internal pullup device may be enabled for
that channel. See
12.5.3 Port D Input Pullup Enable Register.
Figure 18-3
summarizes the timer registers.
NOTE
References to either timer 1 or timer 2 may be made in the following text by
omitting the timer number. For example, TSC may generically refer to both
T1SC and T2SC.