
Serial Peripheral Interface (SPI) Module
Data Sheet
MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A
244
Serial Peripheral Interface (SPI) Module
MOTOROLA
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data register
transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt
request if SPTIE in the SPI control register is set also.
NOTE:
Do not write to the SPI data register unless SPTE is high.
During an SPTE CPU interrupt, the CPU clears SPTE by writing to the transmit
data register.
Reset sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set, allows the MODF flag to be set. If the MODF flag
is set, clearing MODFEN does not clear the MODF flag. If the SPI is enabled as
a master and the MODFEN bit is 0, then the SS pin is available as a
general-purpose I/O.
If the MODFEN bit is 1, then the SS pin is not available as a general-purpose
I/O. When the SPI is enabled as a slave, the SS pin is not available as a
general-purpose I/O regardless of the value of MODFEN. See 15.11.4 SS If the MODFEN bit is 0, the level of the SS pin does not affect the operation of
an enabled SPI configured as a master. For an enabled SPI configured as a
slave, having MODFEN low only prevents the MODF flag from being set. It does
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as shown in
Table 15-3. SPR1 and SPR0 have no effect in slave mode. Reset clears SPR1
and SPR0.
Use this formula to calculate the SPI baud rate:
Table 15-3. SPI Master Baud Rate Selection
SPR1 and SPR0
Baud Rate Divisor (BD)
00
2
01
8
10
32
11
128
Baud rate =
BUSCLK
BD