
Enhanced Serial Communications Interface (ESCI) Module
I/O Registers
MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A
Data Sheet
MOTOROLA
Enhanced Serial Communications Interface (ESCI) Module
187
13.8.2 ESCI Control Register 2
ESCI control register 2 (SCC2):
Enables these CPU interrupt requests:
–
SCTE bit to generate transmitter CPU interrupt requests
–
TC bit to generate transmitter CPU interrupt requests
–
SCRF bit to generate receiver CPU interrupt requests
–
IDLE bit to generate receiver CPU interrupt requests
Enables the transmitter
Enables the receiver
Enables ESCI wakeup
Transmits ESCI break characters
SCTIE — ESCI Transmit Interrupt Enable Bit
This read/write bit enables the SCTE bit to generate ESCI transmitter CPU
interrupt requests. Setting the SCTIE bit in SCC2 enables the SCTE bit to
generate CPU interrupt requests. Reset clears the SCTIE bit.
1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables the TC bit to generate ESCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.
1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests
SCRIE — ESCI Receive Interrupt Enable Bit
This read/write bit enables the SCRF bit to generate ESCI receiver CPU
interrupt requests. Setting the SCRIE bit in SCC2 enables the SCRF bit to
generate CPU interrupt requests. Reset clears the SCRIE bit.
1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables the IDLE bit to generate ESCI receiver CPU interrupt
requests. Reset clears the ILIE bit.
1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests
Address: $0014
Bit 7
654321
Bit 0
Read:
SCTIE
TCIE
SCRIE
ILIE
TE
RE
RWU
SBK
Write:
Reset:
00000000
Figure 13-11. ESCI Control Register 2 (SCC2)