參數(shù)資料
型號： MC68HC811D3VFB4
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： ROM-based high-performance microcontrollers
中文描述： 基于ROM的高性能微控制器
文件頁數(shù)： 17/124頁
文件大小： 840K
代理商： MC68HC811D3VFB4
PIN DESCRIPTIONS
TECHNICAL DATA
2-5
sensitive, it can be connected to a multiple-source wired-OR network with an external
pullup resistor to V
DD
. XIRQ is often used as a power loss detect interrupt.
Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ must be config-
ured for level-sensitive operation if there is more than one source of IRQ interrupt),
each source must drive the interrupt input with an open-drain type of driver to avoid
contention between outputs. There should be a single pullup resistor near the MCU
interrupt input pin (typically 4.7 k
). There must also be an interlock mechanism at
each interrupt source so that the source holds the interrupt line low until the MCU rec-
ognizes and acknowledges the interrupt request. If one or more interrupt sources are
still pending after the MCU services a request, the interrupt line will still be held low
and the MCU will be interrupted again as soon as the interrupt mask bit in the MCU is
cleared (normally upon return from an interrupt). Refer to
SECTION 5 RESETS AND
INTERRUPTS
.
2.7 MODA and MODB (MODA/LIR,and MODB/V
STBY
)
During reset, MODA and MODB select one of the four operating modes. Refer to
SEC-
TION 4 OPERATING MODES AND ON-CHIP MEMORY
.
After the operating mode has been selected, the LIR pin provides an open-drain output
to indicate that execution of an instruction has begun. A series of E-clock cycles occurs
during execution of each instruction. The LIR signal goes low during the first E-clock
cycle of each instruction (opcode fetch). This output is provided for assistance in pro-
gram debugging.
The V
STBY
pin is used to input RAM standby power. When the voltage on this pin is
more than one MOS threshold (about 0.7 volts) above the V
DD
voltage, the internal
192-byte RAM and part of the reset logic are powered from this signal rather than the
V
DD
input. This allows RAM contents to be retained without V
DD
power applied to the
MCU.
Reset must be driven low before V
DD
is removed and must remain low until V
DD
has been restored to a valid level.
2.8 PD6/AS
This pin performs either of two separate functions, depending on the operating mode.
In single-chip and bootstrap modes, the pin functions as input/output port D bit 6. In
the expanded multiplexed and test modes, it provides an address strobe (AS) function.
The AS can demultiplex the address and data signals at port C. Refer to
SECTION 4
OPERATING MODES AND ON-CHIP MEMORY
for further information.
2.9 PD7/R/W
This pin provides two separate functions, depending on the operating mode. In single-
chip and bootstrap modes, PD7/R/W acts as input/output port D bit 7. Refer to
SEC-
TION 6 PARALLEL I/O
for further information.
In expanded multiplexed and test modes, PD7/R/W performs a read/write function.
PD7/R/W controls the direction of transfers on the external data bus. A high on this pin
indicates that a read cycle is in progress.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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