參數(shù)資料
型號: MC68HC805P18P
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, EEPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 85/144頁
文件大小: 1292K
代理商: MC68HC805P18P
Interrupts
Interrupt Types
MC68HC(8)05P18 — Rev. 2.0
Advance Information
MOTOROLA
Interrupts
45
4.3.3.1 External Interrupt (IRQ)
The IRQ pin drives an asynchronous interrupt to the CPU. An edge
detector flip-flop is latched on the falling edge of IRQ. If either the output
from the internal edge detector flip-flop or the level on the IRQ pin is low,
a request is synchronized to the CPU to generate the IRQ interrupt. If the
edge-sensitive only option is selected, the output of the internal edge
detector flip-flop is sampled and the input level on the IRQ pin is ignored.
If port A interrupts are programmed as an option, a port A interrupt will
use the same vector. The interrupt service routine address is specified
by the contents of memory locations $3FFA and $3FFB.
NOTE:
The internal interrupt latch is cleared nine PH2 clock cycles after the
interrupt is recognized (after location $3FFA is read). Therefore, another
external interrupt pulse could be latched during the IRQ service routine.
When the edge- and level-sensitive option is selected, the voltage
applied to the IRQ pin must return to the high state before the RTI
instruction in the interrupt service routine is executed.
The IRQ pin is one source of an IRQ interrupt and a mask option can
also enable the port A pins (PA0–PA7) to act as other IRQ interrupt
sources. These sources are all combined into a single ORing function to
be latched by the IRQ latch.
Figure 4-2. IRQ Function Block Diagram
IRQ
LATCH
R
VDD
IRQ PIN
MASK OPTION
(IRQ LEVEL)
TO IRQ
PROCESSING
IN CPU
TO BIH & BIL
INSTRUCTION
SENSING
:
RST
IRQ VECTOR FETCH
PA7
DDRA7
PA0
DDRA0
PA0 IRQ INHIBIT
(MASK OPTION)
PA7 IRQ INHIBIT
(MASK OPTION)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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