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Operating Modes and On-Chip Memory
Data Sheet
M68HC11E Family — Rev. 5
50
Operating Modes and On-Chip Memory
MOTOROLA
NOSEC — Security Disable Bit
NOSEC is invalid unless the security mask option is specified before the MCU
is manufactured. If the security mask option is omitted NOSEC always reads 1.
The enhanced security feature is available in the MC68S711E9 MCU. The
enhancement to the standard security feature protects the EPROM as well as
RAM and EEPROM.
0 = Security enabled
1 = Security disabled
NOCOP — COP System Disable Bit
1 = COP disabled
0 = COP enabled
ROMON — ROM/EPROM/OTPROM Enable Bit
When this bit is 0, the ROM or EPROM is disabled and that memory space
becomes externally addressed. In single-chip mode, ROMON is forced to 1 to
enable ROM/EPROM regardless of the state of the ROMON bit.
0 = ROM disabled from the memory map
1 = ROM present in the memory map
EEON — EEPROM Enable Bit
When this bit is 0, the EEPROM is disabled and that memory space becomes
externally addressed.
0 = EEPROM removed from the memory map
1 = EEPROM present in the memory map
2.3.3.2 RAM and I/O Mapping Register
The internal registers used to control the operation of the MCU can be relocated
on 4-Kbyte boundaries within the memory space with the use of the RAM and I/O
mapping register (INIT). This 8-bit special-purpose register can change the default
locations of the RAM and control registers within the MCU memory map. It can be
written only once within the first 64 E-clock cycles after a reset in normal modes,
and then it becomes a read-only register.
RAM[3:0] — RAM Map Position Bits
These four bits, which specify the upper hexadecimal digit of the RAM address,
control position of RAM in the memory map. RAM can be positioned at the
beginning of any 4-Kbyte page in the memory map. It is initialized to address
Address: $103D
Bit 7
654321
Bit 0
Read:
RAM3
RAM2
RAM1
RAM0
REG3
REG2
REG1
REG0
Write:
Reset:
00000001
Figure 2-12. RAM and I/O Mapping Register (INIT)