參數(shù)資料
型號: MC68HC705V8CFU
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64
封裝: QFP-64
文件頁數(shù): 145/172頁
文件大?。?/td> 615K
代理商: MC68HC705V8CFU
SECTION 8: LOW-POWER MODES
MOTOROLA
Page 63
MC68HC705V8 Specification Rev. 2.1
SECTION 8
LOW-POWER MODES
The MC68HC705V8 is capable of running in one of several low-power operational modes.
The WAIT and STOP instructions provide two modes that reduce the power required for the
MCU by stopping various internal clocks and/or the on-chip oscillator. The STOP and WAIT
instructions are not normally used if the COP Watchdog Timer is enabled. A mask option
is provided to convert the STOP instruction to an internal reset. The ow of the STOP and
WAIT modes is shown in Figure 8-2.
8.1
STOP INSTRUCTION
The STOP instruction can result in one of two operations depending on the state of the
MOR’s STOP bit. If the STOP option is enabled, the STOP instruction operates like the
STOP in normal MC68HC05 family members and places the device in the low power STOP
Mode. If the STOP option is disabled, the STOP instruction will cause a chip reset when
executed.
8.1.1
STOP MODE
Execution of the STOP instruction, with the proper mask option, places the MCU in its
lowest power consumption mode. In the STOP Mode the internal oscillator is turned off,
halting
all internal processing, including the COP Watchdog Timer.
During the STOP mode, the TCR bits are altered to remove any pending timer interrupt
request and to disable any further timer interrupts. The timer prescaler is cleared. The I bit
in the CCR is cleared and the IRQE mask is set in the ICSR to enable external interrupts.
All other registers and memory remain unaltered. All input/output lines remain unchanged.
The processor can be brought out of the STOP mode only by an external interrupt or reset.
The MCU can be brought out of the STOP Mode by only one of the following:
IRQ pin external interrupt
Externally generated RESET
Falling edge on any Port A or Port C pin (if enabled)
Rising edge on the MDLC BUS pin
When exiting the STOP Mode, the internal oscillator will resume after a 4064 internal
processor clock cycle oscillator stabilization delay, as shown in Figure 8-1.
NOTE:
Execution of the STOP instruction with the proper mask option will cause
the oscillator to stop and therefore disable the COP Watchdog Timer. If
the COP Watchdog Timer is to be used, the STOP Mode should be
disabled by selecting the proper mask option. See 6.2.3.4 COP
WATCHDOG TIMER CONSIDERATIONS for more details.
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