參數(shù)資料
型號: MC68HC705P6ACP
廠商: Freescale Semiconductor
文件頁數(shù): 44/98頁
文件大?。?/td> 0K
描述: IC MCU 2.1MHZ 4.5K OTP 28-DIP
標準包裝: 13
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SIO
外圍設備: POR,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 4.5KB(4.5K x 8)
程序存儲器類型: OTP
RAM 容量: 176 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 4x8b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.600",15.24mm)
包裝: 管件
Timer I/O Registers
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Freescale Semiconductor
49
8.3.3 Timer Registers
The timer registers (TRH and TRL), shown in Figure 8-4, contains the current high and low bytes of the
16-bit counter. Reading TRH before reading TRL causes TRL to be latched until TRL is read. Reading
TRL after reading the timer status register clears the timer overflow flag (TOF). Writing to the timer
registers has no effect.
8.3.4 Alternate Timer Registers
The alternate timer registers (ATRH and ATRL), shown in Figure 8-5, contain the current high and low
bytes of the 16-bit counter. Reading ATRH before reading ATRL causes ATRL to be latched until ATRL
is read. Reading ATRL has no effect on the timer overflow flag (TOF). Writing to the alternate timer
registers has no effect.
NOTE
To prevent interrupts from occurring between readings of ATRH and ATRL,
set the interrupt flag in the condition code register before reading ATRH,
and clear the flag after reading ATRL.
Address:
TRH — $0018
Bit 7
654321
Bit 0
Read:
TRH7
TRH6
TRH5
TRH4
TRH3
TRH2
TRH1
TRH0
Write
Reset:
11111111
Address:
TRL — $0019
Bit 7
654321
Bit 0
Write:
Reset:
11111100
= Unimplemented
Figure 8-4. Timer Registers (TRH and TRL)
Address:
ATRH — $001A
Bit 7
654321
Bit 0
Read:
ACRH7
ACRH6
ACRH5
ACRH4
ACRH3
ACRH2
ACRH1
ACRH0
Write:
Reset:
11111111
Address:
ATRL — $001B
Bit 7
654321
Bit 0
Write:
Reset:
11111100
= Unimplemented
Figure 8-5. Alternate Timer Registers (ATRH and ATRL)
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