參數(shù)資料
型號： MC68HC705JP7CDW
廠商： Freescale Semiconductor
文件頁數(shù)： 141/164頁
文件大小： 0K
描述： IC MCU 8BIT 28-SOIC
標準包裝： 26
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 22
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Analog Subsystem
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
78
Freescale Semiconductor
ICEN
This is a read/write bit that enables a voltage comparison to trigger the input capture register of the
programmable timer when the CPF2 flag bit is set. Therefore, an A/D conversion could be started by
receiving an OCF or TOF from the programmable timer and then terminated when the voltage on the
external ramping capacitor reaches the level of the unknown voltage. The time of termination will be
stored in the 16-bit buffer located at $0014 and $0015. This bit is automatically set whenever mode 2
or 3 is selected by setting the ATD2 control bit. This bit is cleared by a reset of the device.
1 = Connects the CPF2 flag bit to the timer input capture register
0 = Connects the PB3/AN3 pin to the timer input capture register
NOTE
For the input capture to occur when the output of comparator 2 goes high,
the IEDG bit in the TCR must also be set.
When the ICEN bit is set, the input capture function of the programmable
timer is not connected to the PB3/AN3/TCAP pin but is driven by the CPF2
output flag from comparator 2. To return to capturing times from external
events, the ICEN bit must first be cleared before the timed event occurs.
CPIE
This is a read/write bit that enables an analog interrupt when either of the CPF1 or CPF2 flag bits is
set to a logic 1. This bit is cleared by a reset of the device.
1 = Enables analog interrupts when comparator flag bits are set
0 = Disables analog interrupts when comparator flag bits are set
NOTE
If both the ICEN and CPIE bits are set, they will both generate an interrupt
by different paths. One will be the programmable timer interrupt due to the
input capture and the other will be the analog interrupt due to the output of
comparator 2 going high. In this case, the input capture interrupt will be
entered first due to its higher priority. The analog interrupt will then need to
be serviced even if the comparator 2 output has been reset or the input
capture flag (ICF) has been cleared.
CP2EN
The CP2EN enable bit controls power to voltage comparator 2 in the analog subsystem. Powering
down a comparator will drop the supply current. This bit is cleared by a reset of the device.
1 = Writing a logic 1 powers up voltage comparator 2.
0 = Writing a logic 0 powers down voltage comparator 2.
NOTE
Voltage comparators power up slower than digital logic and their outputs
may go through indeterminate states which might set their respective flags
(CPF1, CPF2). It is therefore recommended to power up the charge current
source first (ISEN), then to power up any comparators, and finally clear the
flag bits by writing a logic 1 to the respective CPFR1 or CPFR2 bits in the
ACR.
CP1EN
The CP1EN enable bit will power down the voltage comparator 1 in the analog subsystem. Powering
down a comparator will drop the supply current. This bit is cleared by a reset of the device.
1 = Writing a logic 1 powers up voltage comparator 1
0 = Writing a logic 0 powers down voltage comparator 1
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參數(shù)描述
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