參數(shù)資料
型號： MC68HC705JJ7CDW
廠商： Freescale Semiconductor
文件頁數(shù)： 14/164頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 20-SOIC
標準包裝： 38
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 2.1MHz
連通性： SIO
外圍設備： POR，溫度傳感器，WDT
輸入/輸出數(shù)： 14
程序存儲器容量： 6KB（6K x 8）
程序存儲器類型： OTP
RAM 容量： 224 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
包裝： 管件
Programmable Timer
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
110
Freescale Semiconductor
The input capture registers are made up of two 8-bit read-only registers (ICRH and ICRL) as shown in
Figure 11-7. The input capture edge detector contains a Schmitt trigger to improve noise immunity. The
edge that triggers the counter transfer is defined by the input edge bit (IEDG) in the TCR. Reset does not
affect the contents of the input capture registers.
The result obtained by an input capture will be one count higher than the value of the free-running timer
counter preceding the external transition. This delay is required for internal synchronization. Resolution
is affected by the prescaler, allowing the free-running timer counter to increment once every four internal
clock cycles (eight oscillator clock cycles).
Reading the ICRH inhibits future captures until the ICRL is also read. Reading the ICRL after reading the
timer status register (TSR) clears the ICF flag bit. There is no conflict between reading the ICRL and
transfers from the free-running timer counters. The input capture registers always contain the free-running
timer counter value which corresponds to the most recent input capture.
NOTE
To prevent interrupts from occurring between readings of the ICRH and
ICRL, set the I bit in the condition code register (CCR) before reading ICRH
and clear the I bit after reading ICRL.
11.5 Output Compare Registers
The output compare function is a means of generating an output signal when the 16-bit timer counter
reaches a selected value as shown in Figure 11-8. Software writes the selected value into the output
compare registers. On every fourth internal clock cycle (every eight oscillator clock cycles) the output
compare circuitry compares the value of the free-running timer counter to the value written in the output
compare registers. When a match occurs, the timer transfers the output level (OLVL) from the timer
control register (TCR) to the PB4/AN4/TCMP pin.
Software can use the output compare register to measure time periods, to generate timing delays, or to
generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the
PB4/AN4/TCMP pin.
The planned action on the PB4/AN4/TCMP pin depends on the value stored in the OLVL bit in the TCR,
and it occurs when the value of the 16-bit free-running timer counter matches the value in the output
compare registers shown in Figure 11-9. These registers are read/write bits and are unaffected by reset.
Address:
$0014
Bit 7
654321
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
Unaffected by reset
Address:
$0015
Bit 7
654321
Bit 0
Read:
Bit 7
654321
Bit 0
Write:
Reset:
Unaffected by reset
= Unimplemented
Figure 11-7. Input Capture Registers (ICRH and ICRL)
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