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參數(shù)資料
型號(hào): MC68HC705J1ACP
廠商: Freescale Semiconductor
文件頁數(shù): 5/162頁
文件大?。?/td> 0K
描述: IC MCU 4MHZ 1.2K OTP 20-DIP
標(biāo)準(zhǔn)包裝: 18
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 4MHz
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 14
程序存儲(chǔ)器容量: 1.2KB(1.2K x 8)
程序存儲(chǔ)器類型: OTP
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-DIP(0.300",7.62mm)
包裝: 管件
Technical Data
MC68HC705J1A — Rev. 4.0
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
8.3 Operation
The interrupt request/programming voltage pin (IRQ/VPP) and port A
pins 0–3 (PA0–PA3) provide external interrupts. The PIRQ bit in the
mask option register (MOR) enables PA0–PA3 as IRQ interrupt sources,
which are combined into a single ORing function to be latched by the
IRQ latch. Figure 8-1 shows the structure of the IRQ module.
After completing its current instruction, the CPU tests the IRQ latch. If the
IRQ latch is set, the CPU then tests the I bit in the condition code register
and the IRQE bit in the IRQ status and control register. If the
I bit is clear and the IRQE bit is set, the CPU then begins the interrupt
sequence. This interrupt is serviced by the interrupt service routine
located at $07FA and $07FB.
The CPU clears the IRQ latch while it fetches the interrupt vector, so that
another external interrupt request can be latched during the interrupt
service routine. As soon as the I bit is cleared during the return from
interrupt, the CPU can recognize the new interrupt request. Figure 8-2
shows the sequence of events caused by an interrupt.
Figure 8-1. IRQ Module Block Diagram
PIRQ
LEVEL-SENSITIVE TRIGGER
PA3
PA2
PA1
IRQ
PA0
VDD
(MOR LEVEL BIT)
RESET
IRQ VECTOR FETCH
EXTERNAL
INTERRUPT
REQUEST
(MOR)
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQF
IRQR
IRQE
DQ
CK
IRQ
CLR
LATCH
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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