參數(shù)資料
型號(hào): MC68HC11F1MFN1
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: ROM-based high-performance microcontrollers
中文描述: 基于ROM的高性能微控制器
文件頁(yè)數(shù): 97/124頁(yè)
文件大?。?/td> 840K
代理商: MC68HC11F1MFN1
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TIMING SYSTEM
TECHNICAL DATA
9-11
polled or interrupt driven system. Each bit of TFLG1 corresponds to a bit in TMSK1 in
the same position.
Clear flags by writing a one to the corresponding bit position(s).
OC1F–OC5F — Output Compare x Flag
Set each time the counter matches output compare x value
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
IC1F–IC3F — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line
9.3.9 Timer Interrupt Mask 2 Register
Use this 8-bit register to enable or inhibit timer overflow and real-time interrupts. The
timer prescaler control bits are included in this register.
TOI — Timer Overflow Interrupt Enable
0 = TOF interrupts disabled
1 = Interrupt requested when TOF is set to one
RTII — Real-time Interrupt Enable
Refer to
9.4 Real-Time Interrupt
.
PAOVI — Pulse Accumulator Overflow Interrupt Enable
Refer to
9.6 Pulse Accumulator
.
PAII — Pulse Accumulator Input Edge Interrupt Enable
Refer to
9.6 Pulse Accumulator
.
NOTE
Bits in TMSK2 correspond bit for bit with flag bits in TFLG2. Ones in
TMSK2 enable the corresponding interrupt sources.
TFLG1
— Timer Interrupt Flag 1
$0023
Bit 7
OC1F
0
6
5
4
3
2
1
Bit 0
IC3F
0
OC2F
0
OC3F
0
OC4F
0
I4/O5F
0
IC1F
0
IC2F
0
RESET:
TMSK2
— Timer Interrupt Mask 2
$0024
Bit 7
TOI
0
6
5
4
3
0
0
2
0
0
1
Bit 0
PR0
0
RTII
0
PAOVI
0
PAII
0
PR1
0
RESET:
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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