參數(shù)資料
型號： MC68HC11F1FN4
廠商： 飛思卡爾半導體(中國)有限公司
英文描述： ROM-based high-performance microcontrollers
中文描述： 基于ROM的高性能微控制器
文件頁數(shù)： 104/124頁
文件大小： 840K
代理商： MC68HC11F1FN4
TIMING SYSTEM
9-18
TECHNICAL DATA
9.6.3 Pulse Accumulator Status and Interrupt Bits
The pulse accumulator control bits, PAOVI and PAII, PAOVF, and PAIF are located
within timer registers TMSK2 and TFLG2.
PAOVI and PAOVF — Pulse Accumulator Interrupt Enable and Overflow Flag
The PAOVF status bit is set each time the pulse accumulator count rolls over from $FF
to $00. To clear this status bit, write a one in the corresponding data bit position (bit 5)
of the TFLG2 register. The PAOVI control bit allows configuring the pulse accumulator
overflow for polled or interrupt-driven operation and does not affect the state of
PAOVF. When PAOVI is zero, pulse accumulator overflow interrupts are inhibited, and
the system operates in a polled mode, which requires PAOVF to be polled by user soft-
ware to determine when an overflow has occurred. When the PAOVI control bit is set,
a hardware interrupt request is generated each time PAOVF is set. Before leaving the
interrupt service routine, software must clear PAOVF by writing to the TFLG2 register.
PAII and PAIF — Pulse Accumulator Input Edge Interrupt Enable and Flag
The PAIF status bit is automatically set each time a selected edge is detected at the
PA7/PAI/OC1 pin. To clear this status bit, write to the TFLG2 register with a one in the
corresponding data bit position (bit 4). The PAII control bit allows configuring the pulse
accumulator input edge detect for polled or interrupt-driven operation but does not af-
fect setting or clearing the PAIF bit. When PAII is zero, pulse accumulator input inter-
rupts are inhibited, and the system operates in a polled mode. In this mode, the PAIF
bit must be polled by user software to determine when an edge has occurred. When
the PAII control bit is set, a hardware interrupt request is generated each time PAIF is
set. Before leaving the interrupt service routine, software must clear PAIF by writing to
the TFLG register.
TMSK2
— Timer Interrupt Mask 2
PACNT
— Pulse Accumulator Count
$0027
Bit 7
Bit 7
6
6
5
5
4
4
3
3
2
2
1
1
Bit 0
Bit 0
$0024
Bit 7
TOI
0
6
5
4
3
0
0
2
0
0
1
Bit 0
PR0
0
RTII
0
PAOVI
0
PAII
0
PR1
0
RESET:
TFLG2
— Timer Interrupt Flag 2
$0025
Bit 7
TOF
0
6
5
4
3
0
0
2
0
0
1
0
0
Bit 0
0
0
RTIF
0
PAOVF
0
PAIF
0
RESET:
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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