- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359653 > MC68HC11F1FB (飛思卡爾半導(dǎo)體(中國)有限公司) ROM-based high-performance microcontrollers PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC11F1FB |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | ROM-based high-performance microcontrollers |
| 中文描述： | 基于ROM的高性能微控制器 |
| 文件頁數(shù)： | 55/124頁 |
| 文件大?。?/td> | 840K |
| 代理商： | MC68HC11F1FB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁當(dāng)前第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁
RESETS AND INTERRUPTS
TECHNICAL DATA
5-11
The stacked return address can be used as a pointer to the illegal opcode so the illegal
opcode service routine can evaluate the offending opcode.
5.4.4 Software Interrupt
SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhib-
ited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit,
once an SWI interrupt begins, other interrupts are inhibited until SWI is complete, or
until user software clears the I bit in the CCR.
5.4.5 Maskable Interrupts
The maskable interrupt structure of the MCU can be extended to include additional ex-
ternal interrupt sources through the IRQ pin. The default configuration of this pin is a
low-level sensitive wired-OR network. When an event triggers an interrupt, a software
accessible interrupt flag is set. When enabled, this flag causes a constant request for
interrupt service. After the flag is cleared, the service request is released.
5.4.6 Reset and Interrupt Processing
Figure 5-1
and
Figure 5-1
illustrate the reset and interrupt process.
Figure 5-1
illus-
trates how the CPU begins from a reset and how interrupt detection relates to normal
opcode fetches.
Figure 5-1
is an expansion of a block in
Figure 5-1
and illustrates in-
terrupt priorities.
Figure 5-2
shows the resolution of interrupt sources within the SCI
subsystem.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC68HC11F1FB1 | ROM-based high-performance microcontrollers |
| MC68HC11F1FB3 | ROM-based high-performance microcontrollers |
| MC68HC11F1FB4 | ROM-based high-performance microcontrollers |
| MC68HC11F1VFU3 | ROM-based high-performance microcontrollers |
| MC68HC11F1VFU4 | ROM-based high-performance microcontrollers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11F1FB1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11F1FB3 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11F1FB4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
| MC68HC11F1FN | 制造商:Motorola Inc 功能描述: |
| MC68HC11F1FN1 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:ROM-based high-performance microcontrollers |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。