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參數(shù)資料
| 型號： | MC68HC11F1FB4 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | ROM-based high-performance microcontrollers |
| 中文描述： | 基于ROM的高性能微控制器 |
| 文件頁數(shù)： | 44/124頁 |
| 文件大?。?/td> | 840K |
| 代理商： | MC68HC11F1FB4 |
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OPERATING MODES AND ON-CHIP MEMORY
For More Information On This Product,
Go to: www.freescale.com
4-10
TECHNICAL DATA
4.2.2.3 OPTION Register
The 8-bit special-purpose OPTION register sets internal system configuration options
during initialization. The time protected control bits, IRQE, DLY, and CR[1:0] can be
written to only once after a reset and then they become read-only. This minimizes the
possibility of any accidental changes to the system configuration.
*Can be written only once in first 64 cycles out of reset in normal modes, or at any time in special modes
Bits [7:6] and 2 — Not implemented
Always read zero
IRQE — IRQ
Select Edge Sensitive only
0 = IRQ
is configured for level sensitive operation
1 = IRQ
is configured for edge sensitive only operation
DLY — Enable Oscillator Startup Delay
0 = The oscillator startup delay coming out of STOP is bypassed and the MCU re-
sumes processing within about four bus cycles.
1 = A delay of approximately 4000 E-clock cycles is imposed as the MCU is started
up from the STOP power-saving mode. This delay allows the crystal oscillator
to stabilize.
CME — Clock Monitor Enable
Refer to
SECTION 5 RESETS AND INTERRUPTS
.
CR[1:0] — COP Timer Rate Select Bits
The internal E clock is first divided by 2
15
before it enters the COP watchdog system.
These control bits determine a scaling factor for the watchdog timer. Refer to
SEC-
TION 5 RESETS AND INTERRUPTS
.
OPTION
— System Configuration Options
Bit 7
0
RESET:
0
$0039
Bit 0
CR0*
0
6
0
0
5
4
3
2
0
0
1
IRQE*
0
DLY*
1
CME
0
CR1*
0
F
Freescale Semiconductor, Inc.
n
.
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