參數(shù)資料
型號(hào): MC68HC11D3FB
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: ROM-based high-performance microcontrollers
中文描述: 基于ROM的高性能微控制器
文件頁數(shù): 64/124頁
文件大小: 840K
代理商: MC68HC11D3FB
PARALLEL I/O
6-2
TECHNICAL DATA
DDB[7:0] — Data Direction for Port B
0 = Corresponding port B pin configured for input only
1 = Corresponding port B pin configured as output
6.3 Port C
Port C pins are general-purpose I/O (PC[7:0]) in single-chip mode. In expanded mul-
tiplexed mode, port C pins are configured as multiplexed address/data pins. During the
data cycle, bits [7:0] (PC[7:0]) are bidirectional data pins controlled by the R/W signal.
DDC[7:0] — Data Direction for Port C
0 = Input
1 = Output
6.4 Port D
The eight port D bits (PD[7:0]) can be used for general-purpose I/O, for the SCI and
SPI subsystems, or for bus data direction control. Port D can be read at any time. In-
puts return the sensed levels at the pin; outputs return the input level of the port D pin
drivers. If port D is written, the data is stored in an internal latch, and can be driven only
if port D is configured for general-purpose output. This port shares functions with the
on-chip SCI and SPI subsystems, while bits 6 and 7 control the direction of data flow
on the bus in expanded and special test modes.
DDRB
— Data Direction Register for Port B
$0006
Bit 7
DDB7
0
6
5
4
3
2
1
Bit 0
DDB0
0
DDB6
0
DDB5
0
DDC4
0
DDB3
0
DDB2
0
DDB1
0
RESET:
PORTC
— Port C Data
$0003
Bit 7
PC7
6
5
4
3
2
1
Bit 0
PC0
PC6
PC5
PC4
PC3
PC2
PC1
S. Chip
or Boot:
RESET:
Expan.
or Test:
RESET:
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Reset configures pins as HiZ inputs
ADDR5/
DATA5
DATA4
Reset configures pins as multiplexed, low-order address/data I/O
ADDR7/
DATA7
ADDR6/
DATA6
ADDR4/
ADDR3/
DATA3
ADDR2/
DATA2
ADDR1/
DATA1
ADDR0/
DATA0
DDRC
— Data Direction Register for Port C
$0007
Bit 7
DDC7
0
6
5
4
3
2
1
Bit 0
DDC0
0
DDC6
0
DDC5
0
DDC4
0
DDC3
0
DDC2
0
DDC1
0
RESET:
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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