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參數(shù)資料
| 型號(hào)： | MC68HC11D3CP1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PDIP40 |
| 封裝： | PLASTIC, DIP-40 |
| 文件頁(yè)數(shù)： | 90/124頁(yè) |
| 文件大小： | 6875K |
| 代理商： | MC68HC11D3CP1 |
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SERIAL COMMUNICATIONS INTERFACE
7-2
TECHNICAL DATA
Figure 7-1 SCI Transmitter Block Diagram
7.3 Receive Operation
During receive operations, the transmit sequence is reversed. The serial shift register
receives data and transfers it to a parallel receive data register (SCDR) as a complete
word. Refer to Figure 7-2. This double buffered operation allows a character to be
shifted in serially while another character is already in the SCDR. An advanced data
11 SCI TX BLOCK
FE
NF
OR
IDLE
RDRF
TC
TD
R
E
SCSRINTERRUPT STATUS
SBK
RWU
RE
TE
IL
IE
RIE
TC
IE
TI
E
SCCR2 SCI CONTROL 2
TRANSMITTER
CONTROL LOGIC
TCIE
TC
TIE
TDRE
SCI Rx
REQUESTS
SCI INTERRUPT
REQUEST
INTERNAL
DATA BUS
PIN BUFFER
AND CONTROL
H (8) 76543210L
10 (11) - BIT Tx SHIFT REGISTER
DDD1
PD1
TxD
SCDR Tx BUFFER
T
R
ANSFE
R
T
x
B
U
FFE
R
SHI
F
T
ENA
B
L
E
JAM
ENA
B
L
E
PR
E
A
M
BL
E
—
J
A
M
1
s
BREAK
—
J
AM
0
s
(WRITE ONLY)
FORCE PIN
DIRECTION (OUT)
SI
ZE
8
/9
WAKE
M
T8
R8
SCCR1 SCI CONTROL 1
TRANSMITTER
BAUD RATE
CLOCK
8
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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