- 您現(xiàn)在的位置：買賣IC網 > PDF目錄45225 > MC68HC11A1MP2 (ABILIS SYSTEMS) 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48 PDF資料下載
參數(shù)資料
| 型號： | MC68HC11A1MP2 |
| 廠商： | ABILIS SYSTEMS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48 |
| 封裝： | PLASTIC, DIP-48 |
| 文件頁數(shù)： | 101/158頁 |
| 文件大?。?/td> | 3803K |
| 代理商： | MC68HC11A1MP2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁當前第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
TECHNICAL DATA
5-3
5
Once a valid start bit is detected, the start bit, each data bit, and the stop bit are sam-
pled three times at RT intervals 8 RT, 9 RT, and 10 RT (1 RT is the position where the
bit is expected to start), as shown in Figure 5-2. The value of the bit is determined by
voting logic which takes the value of the majority of samples.
Figure 5-2 Sampling Technique Used on All Bits
5.5 Start Bit Detection
When the RxD input is detected low, it is tested for three more sample times (referred
to as the start edge verification samples in Figure 5-3). If at least two of these three
verification samples detect a logic zero, a valid start bit has been detected, otherwise
the line is assumed to be idle. A noise flag is set if all three verification samples do not
detect a logic zero. A valid start bit could be assumed with a set noise flag present.
If there has been a framing error without detection of a break (10 zeros for 8-bit format
or 11 zeros for 9-bit format), the circuit continues to operate as if there actually was a
stop bit and the start edge will be placed artificially. The last bit received in the data
shift register is inverted to a logic one, and the three logic one start qualifiers (shown
in Figure 5-3) are forced into the sample shift register during the interval when detec-
tion of a start bit is anticipated (see Figure 5-4); therefore, the start bit will be accepted
no sooner than it is anticipated.
If the receiver detects that a break produced the framing error, the start bit will not be
artificially induced and the receiver must actually detect a logic one before the start bit
can be recognized. See Figure 5-5.
16
1
8
9
10
RxD
SCI BIT SAMPLING
PREVIOUS BIT
PRESENT BIT
NEXT BIT
SAMPLES
16
1
vvv
R
RRR
R
T
TTT
T
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關PDF資料 |
PDF描述 |
|---|---|
| MC68HC11A8VCFN2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| MC68HC11A1VP2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48 |
| MC68HC11A1CFN2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQCC52 |
| MC68HC11A1CFU2 | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP64 |
| MC68HCP11A1CFN3 | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC52 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC11A1P | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers |
| MC68HC11A1VFN | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:8-Bit Microcontrollers |
| MC68HC11A1VFN2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A1VFU2 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS Single-Chip Microcontroller |
| MC68HC11A1VP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8-Bit Microcontrollers |
發(fā)布緊急采購，3分鐘左右您將得到回復。