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參數(shù)資料
| 型號(hào)： | MC68HC11A0MFN4 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | ROM-based high-performance microcontrollers |
| 中文描述： | 基于ROM的高性能微控制器 |
| 文件頁數(shù)： | 89/124頁 |
| 文件大?。?/td> | 840K |
| 代理商： | MC68HC11A0MFN4 |
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TIMING SYSTEM
TECHNICAL DATA
9-3
9.1 Timer Structure
Figure 9-1
shows the capture/compare system block diagram. The port A pin control
block includes logic for timer functions and for general-purpose I/O. For pins PA2,
PA1, and PA0, this block contains both the edge-detection logic and the control logic
that enables the selection of which edge triggers an input capture. The digital level on
PA[2:0] can be read at any time (read PORTA register), even if the pin is being used
for the input capture function. Pins PA[6:4] are used for either general-purpose output,
or as output compare pins. Pin PA3 can be used for general-purpose I/O, input capture
4, output compare 5, or output compare 1. When one of these pins is being used for
an output compare function, it cannot be written directly as if it were a general-purpose
output. Each of the output compare functions (OC5–OC2) is related to one of the port
A output pins. Output compare one (OC1) has extra control logic, allowing it optional
control of any combination of the PA[7:3] pins. The PA7 pin can be used as a general-
purpose I/O pin, as an input to the pulse accumulator, or as an OC1 output pin.
Table 9-1 Timer Summary
XTAL Frequencies
8.0 MHz
2.0 MHz
500 ns
Main Timer Count Rates
4.0 MHz
1.0 MHz
1000 ns
12.0 MHz
3.0 MHz
333 ns
Other Rates
(E)
(1/E)
Control
Bits
PR[1:0]
0 0
1 count —
overflow —
0 1
1 count —
overflow —
1 0
1 count —
overflow —
1 1
1 count —
overflow —
1.0 μs
65.536 ms
500 ns
32.768 ms
333 ns
21.845 ms
(E/1)
(E/2
16
)
4.0 μs
262.14 ms
2.0 μs
131.07 ms
1.333 μs
87.381 ms
(E/4)
(E/2
18
)
8.0 μs
524.29 ms
4.0 μs
262.14 ms
2.667 μs
174.76 ms
(E/8)
(E/2
19
)
16.0 μs
1.049 s
8.0 μs
524.29 ms
5.333 μs
349.52 ms
(E/16)
(E/2
20
)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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