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參數資料
| 型號： | MC68HC08QY4CDTE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.65 MM PITCH, LEAD FREE, TSSOP-16 |
| 文件頁數： | 30/176頁 |
| 文件大?。?/td> | 1124K |
| 代理商： | MC68HC08QY4CDTE |
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Interrupts
MC68HC08QY/QT Family Data Sheet, Rev. 2
Freescale Semiconductor
125
14.4 Interrupts
The following TIM sources can generate interrupt requests:
TIM overflow flag (TOF) — The TOF bit is set when the counter reaches the modulo value
programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,
enables TIM overflow interrupt requests. TOF and TOIE are in the TSC register.
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare
occurs on channel x. Channel x TIM interrupt requests are controlled by the channel x interrupt
enable bit, CHxIE. Channel x TIM interrupt requests are enabled when CHxIE =1. CHxF and
CHxIE are in the TSCx register.
14.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-consumption standby modes.
14.5.1 Wait Mode
The TIM remains active after the execution of a WAIT instruction. In wait mode the TIM registers are not
accessible by the CPU. Any enabled interrupt request from the TIM can bring the MCU out of wait mode.
If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before
executing the WAIT instruction.
14.5.2 Stop Mode
The TIM module is inactive after the execution of a STOP instruction. The STOP instruction does not
affect register conditions. TIM operation resumes after an external interrupt. If stop mode is exited by
reset, the TIM is reset.
14.6 TIM During Break Interrupts
A break interrupt stops the counter.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the break flag control register (BFCR) enables software to clear status
bits during the break state. See BFCR in the SIM section of this data sheet.
To allow software to clear status bits during a break interrupt, write a 1 to BCFE. If a status bit is cleared
during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to BCFE. With BCFE cleared (its default state),
software can read and write registers during the break state without affecting status bits. Some status bits
have a two-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is cleared. After the break, doing the
second step clears the status bit.
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