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參數(shù)資料
| 型號： | MC68HC08QY2VDT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.65 MM PITCH, TSSOP-16 |
| 文件頁數(shù)： | 109/178頁 |
| 文件大小： | 2311K |
| 代理商： | MC68HC08QY2VDT |
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10-Bit Analog-to-Digital Converter (ADC10) Module
MC68HC08QY/QT Family Data Sheet, Rev. 1
36
Freescale Semiconductor
3.3.4 Sources of Error
Several sources of error exist for ADC conversions. These are discussed in the following sections.
3.3.4.1 Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given
the maximum input resistance of approximately 15 k
Ω and input capacitance of approximately 10 pF,
sampling to within 1/4LSB (at 10-bit resolution) can be achieved within the minimum sample window (3.5
cycles / 2 MHz maximum ADCK frequency) provided the resistance of the external analog source (RAS)
is kept below 10 k
Ω. Higher source resistances or higher-accuracy sampling is possible by setting
ADLSMP (to increase the sample window to 23.5 cycles) or decreasing ADCK frequency to increase
sample time.
3.3.4.2 Pin Leakage Error
Leakage on the I/O pins can cause conversion error if the external analog source resistance (RAS) is high.
If this error cannot be tolerated by the application, keep RAS lower than VADVIN / (4096*ILeak) for less than
1/4LSB leakage error (at 10-bit resolution).
3.3.4.3 Noise-Induced Errors
System noise which occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC10 accuracy numbers are guaranteed as specified only if the following conditions
are met:
There is a 0.1
μF low-ESR capacitor from V
REFH to VREFL (if available).
There is a 0.1
μF low-ESR capacitor from V
DDA to VSSA (if available).
If inductive isolation is used from the primary supply, an additional 1
μF capacitor is placed from
VDDA to VSSA (if available).
VSSA and VREFL (if available) is connected to VSS at a quiet point in the ground plane.
The MCU is placed in wait mode immediately after initiating the conversion (next instruction after
write to ADCSC).
There is no I/O switching, input or output, on the MCU during the conversion.
There are some situations where external system activity causes radiated or conducted noise emissions
or excessive VDD noise is coupled into the ADC10. In these cases, or when the MCU cannot be placed
in wait or I/O activity cannot be halted, the following recommendations may reduce the effect of noise on
the accuracy:
Place a 0.01
μF capacitor on the selected input channel to V
REFL or VSSA (if available). This will
improve noise issues but will affect sample rate based on the external analog source resistance.
Operate the ADC10 in stop mode by setting ACLKEN, selecting the channel in ADCSC, and
executing a STOP instruction. This will reduce VDD noise but will increase effective conversion time
due to stop recovery.
Average the input by converting the output many times in succession and dividing the sum of the
results. Four samples are required to eliminate the effect of a 1LSB, one-time error.
Reduce the effect of synchronous noise by operating off the asynchronous clock (ACLKEN=1) and
averaging. Noise that is synchronous to the ADCK cannot be averaged out.
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