參數(shù)資料
型號： MC68HC08QY1MDT
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.65 MM PITCH, TSSOP-16
文件頁數(shù)： 29/178頁
文件大小： 2311K
代理商： MC68HC08QY1MDT
Timer Interface Module (TIM)
MC68HC08QY/QT Family Data Sheet, Rev. 1
124
Freescale Semiconductor
channel. Writing to the active channel registers is the same as generating
unbuffered PWM signals.
14.3.4.3 PWM Initialization
To ensure correct operation when generating unbuffered or buffered PWM signals, use the following
initialization procedure:
1.
In the TIM status and control register (TSC):
a.
Stop the counter by setting the TIM stop bit, TSTOP.
b.
Reset the counter and prescaler by setting the TIM reset bit, TRST.
2.
In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM
period.
3.
In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.
4.
In TIM channel x status and control register (TSCx):
a.
Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare
or PWM signals) to the mode select bits, MSxB:MSxA. See Table 14-2.
b.
Write 1 to the toggle-on-overflow bit, TOVx.
c.
Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The output action on compare must
force the output to the complement of the pulse width level. See Table 14-2.
NOTE
In PWM signal generation, do not program the PWM channel to toggle on
output compare. Toggling on output compare prevents reliable 0% duty
cycle generation and removes the ability of the channel to self-correct in the
event of software error or noise. Toggling on output compare can also
cause incorrect PWM signal generation when changing the PWM pulse
width to a new, much larger value.
5.
In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM
channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control
register 0 (TSCR0) controls and monitors the PWM signal from the linked channels. MS0B takes priority
over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output
compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty
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